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s3c880a/f880a 8-bit cmos microcontrollers user's manual revision 3
important notice the information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. s3c880a/f880a 8-bit cmos microcontrollers user's manual, revision 3 publication number: 23-s3-c880a/f880a-072004 ? 2004 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microcontroller business has been awarded full iso-14001 certification (bsi certificate no. fm24653). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, kiheung-eup yongin-city, kyunggi-do, korea c.p.o. box #37, suwon 449-900 tel: (82)-(31)-209-1907 fax: (82)-(31)-209-1889 home-page url: http://www.intl.samsungsemi.com printed in the republic of korea
s3c880a/f880a microcontroller iii preface the s3c880a/f880a microcontroller user's manual is designed for application designers and programmers who are using the s3c880a/f880a microcontroller for application development. it is organized in two main parts: part i programming model part ii hardware descriptions part i contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. it has six chapters: chapter 1 product overview chapter 2 address spaces chapter 3 addressing modes chapter 4 control registers chapter 5 interrupt structure chapter 6 sam8 instruction set chapter 1, "product overview," is a high-level introduction to s3c880a/f880a with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. chapter 2, "address spaces," describes program and data memory spaces, the internal register file, and register addressing. chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. chapter 3, "addressing modes," contains detailed descriptions of the addressing modes that are supported by the s3c8-series cpu. chapter 4, "control registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. you can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. chapter 5, "interrupt structure," describes the s3c880a/f880a interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in part ii. chapter 6, "sam8 instruction set," describes the features and conventions of the instruction set used for all s3c8- series microcontrollers. several summary tables are presented for orientation and reference. detailed descriptions of each instruction are presented in a standard format. each instruction description includes one or more practical examples of how to use the instruction when writing an application program. a basic familiarity with the information in part i will help you to understand the hardware module descriptions in part ii. if you are not yet familiar with the s3c8-series microcontroller family and are reading this manual for the first time, we recommend that you first read chapters 1?3 carefully. then, briefly look over the detailed information in chapters 4, 5, and 6. later, you can reference the information in part i as necessary. part ii "hardware descriptions," has detailed information about specific hardware components of the s3c880a/f880a microcontroller. also included in part ii are electrical, mechanical, mtp, and development tools data. it has 11 chapters: chapter 7 clock circuits chapter 8 n reset and power-down chapter 9 i/o ports chapter 10 basic timer and timer 0 chapter 11 timer a chapter 12 pwm and capture chapter 13 on-screen display (osd) chapter 14 analog-to-digital converter chapter 15 electrical data chapter 16 mechanical data chapter 17 S3F880A mtp chapter 18 development tools two order forms are included at the back of this manual to facilitate customer order for s3c880a/f880a microcontrollers: the mask rom order form, and the mask option selection form. you can photocopy these forms, fill them out, and then forward them to your local samsung sales representative.

s3c880a/f880a microcontroller v table of contents part i ? programming model chapter 1 product overview overview ................................ ................................ ................................ ................................ ............. 1-1 features ................................ ................................ ................................ ................................ ............. 1-2 block diagram ................................ ................................ ................................ ................................ .... 1-3 pin assignments ................................ ................................ ................................ ................................ . 1-4 pin descriptions ................................ ................................ ................................ ................................ .. 1-5 pin circuits ................................ ................................ ................................ ................................ ......... 1-7 chapter 2 address spaces overview ................................ ................................ ................................ ................................ ............. 2-1 program memory (rom) ................................ ................................ ................................ ...................... 2-2 register architecture ................................ ................................ ................................ ........................... 2-3 rom code option (rcod_opt) ................................ ................................ ................................ ........... 2-5 register page pointer (pp) ................................ ................................ ................................ .......... 2-6 effect of different instructions for inter-page data operations ................................ ......................... 2-7 register set 1 ................................ ................................ ................................ ............................. 2-14 register set 2 ................................ ................................ ................................ ............................. 2-14 prime register space ................................ ................................ ................................ .................. 2-14 working registers ................................ ................................ ................................ ....................... 2-16 using the register pointers ................................ ................................ ................................ ......... 2-17 register addressing ................................ ................................ ................................ ............................ 2-19 common working register area (c0h?cfh) ................................ ................................ ................. 2-21 4-bit working register addressing ................................ ................................ ................................ 2-22 8-bit working register addressing ................................ ................................ ................................ 2-24 system and user stacks ................................ ................................ ................................ ..................... 2-26 chapter 3 addressing modes overview ................................ ................................ ................................ ................................ ............. 3-1 register addressing mode (r) ................................ ................................ ................................ ...... 3-2 indirect register addressing mode (ir) ................................ ................................ .......................... 3-3 indexed addressing mode (x) ................................ ................................ ................................ ....... 3-7 direct address mode (da) ................................ ................................ ................................ ............ 3-10 indirect address mode (ia) ................................ ................................ ................................ ........... 3-12 relative address mode (ra) ................................ ................................ ................................ ......... 3-13 immediate mode (im) ................................ ................................ ................................ ................... 3-14
vi s3c880a/f880a micro controller table of contents (continued) chapter 4 control registers overview ................................ ................................ ................................ ................................ ............. 4-1 chapter 5 interrupt structure overview ................................ ................................ ................................ ................................ ............. 5-1 interrupt types ................................ ................................ ................................ ............................ 5-1 s3c880a/f880a interrupt structure ................................ ................................ .............................. 5-2 interrupt vector addresses ................................ ................................ ................................ ........... 5-4 enable/disable interrupt instructions (ei, di) ................................ ................................ .................. 5-6 system-level interrupt control registers ................................ ................................ ....................... 5-6 interrupt processing control points ................................ ................................ ............................... 5-7 peripheral interrupt control registers ................................ ................................ ............................ 5-8 system mode register (sym) ................................ ................................ ................................ ...... 5-9 interrupt mask register (imr) ................................ ................................ ................................ ....... 5-10 interrupt priority register (ipr) ................................ ................................ ................................ ..... 5-11 interrupt request register (irq) ................................ ................................ ................................ ... 5-12 interrupt pending function types ................................ ................................ ................................ .. 5-13 interrupt source polling sequence ................................ ................................ ................................ 5-14 interrupt service routines ................................ ................................ ................................ ............. 5-14 generating interrupt vector addresses ................................ ................................ .......................... 5-15 nesting of vectored interrupts ................................ ................................ ................................ ....... 5-15 instruction pointer (ip) ................................ ................................ ................................ ................. 5-15 fast interrupt processing ................................ ................................ ................................ ............. 5-16 chapter 6 sam8 instruction set overview ................................ ................................ ................................ ................................ ............. 6-1 data types ................................ ................................ ................................ ................................ . 6-1 register addressing ................................ ................................ ................................ .................... 6-1 addressing modes ................................ ................................ ................................ ....................... 6-1 flags register (flags) ................................ ................................ ................................ ............... 6-6 flag descriptions ................................ ................................ ................................ ........................ 6-7 instruction set notation ................................ ................................ ................................ ................ 6-8 condition codes ................................ ................................ ................................ .......................... 6-12 instruction descriptions ................................ ................................ ................................ ................ 6-13
s3c880a/f880a microcontroller vii table of contents (continued) part ii hardware descriptions chapter 7 clock circuit overview ................................ ................................ ................................ ................................ ............. 7-1 system clock circuit ................................ ................................ ................................ ................... 7-1 clock status during power-down modes ................................ ................................ ....................... 7-2 system clock control register (clkcon) ................................ ................................ ..................... 7-3 relation between l-c oscillator and cpu clock ................................ ................................ ............ 7-5 chapter 8 nreset and power-down system reset ................................ ................................ ................................ ................................ ..... 8-1 overview ................................ ................................ ................................ ................................ ..... 8-1 hardware reset values ................................ ................................ ................................ ................ 8-2 power-down modes ................................ ................................ ................................ ............................. 8-5 stop mode ................................ ................................ ................................ ................................ .. 8-5 idle mode ................................ ................................ ................................ ................................ .... 8-6 chapter 9 i/o ports overview ................................ ................................ ................................ ................................ ............. 9-1 port data registers ................................ ................................ ................................ ..................... 9-2 port 0 ................................ ................................ ................................ ................................ ......... 9-2 port 1 ................................ ................................ ................................ ................................ ......... 9-4 port 2 ................................ ................................ ................................ ................................ ......... 9-5 port 3 ................................ ................................ ................................ ................................ ......... 9-6 chapter 10 basic timer and timer 0 module overview ................................ ................................ ................................ ................................ .. 10-1 basic timer control register (btcon) ................................ ................................ .......................... 10-2 basic timer function description ................................ ................................ ................................ .. 10-3 timer 0 control register (t0con) ................................ ................................ ................................ . 10-6 timer 0 function description ................................ ................................ ................................ ........ 10-7
viii s3c880a/f880a microcontroller table of contents (continued) chapter 11 timer a overview ................................ ................................ ................................ ................................ ............. 11-1 timer clock input ................................ ................................ ................................ ........................ 11-1 timer a interrupt control ................................ ................................ ................................ .............. 11-1 timer a function description ................................ ................................ ................................ ........ 11-2 timer a control register (tacon) ................................ ................................ ................................ 11-3 chapter 12 pwm and capture pwm/capture module ................................ ................................ ................................ .......................... 12-1 pwm control register (pwmcon) ................................ ................................ ............................... 12-2 pwm2?pwm5 ................................ ................................ ................................ ................................ .... 12-3 pwm2?pwm5 function description ................................ ................................ ............................. 12-4 staggered pwm outputs ................................ ................................ ................................ ............. 12-5 pwm0?pwm1 ................................ ................................ ................................ ................................ .... 12-7 pwm counter ................................ ................................ ................................ ............................. 12-7 pwm data and extension registers ................................ ................................ ............................. 12-7 pwm clock rate ................................ ................................ ................................ ........................ 12-7 pwm0 and pwm1 function description ................................ ................................ ........................ 12-8 capture unit ................................ ................................ ................................ ................................ 12-12 chapter 13 on-screen display (osd) overview ................................ ................................ ................................ ................................ ............. 13-1 pattern generation software ................................ ................................ ................................ ......... 13-1 internal osd clock ................................ ................................ ................................ ...................... 13-2 osd video ram ................................ ................................ ................................ ......................... 13-2 osd control register overview ................................ ................................ ................................ ............. 13-5 display control register (dspcon) ................................ ................................ .............................. 13-6 character size control register (chacon) ................................ ................................ ................... 13-8 fade-in and fade-out control register (fadecon) ................................ ................................ ....... 13-10 display position control ................................ ................................ ................................ ....................... 13-14 row control register (rowcon) ................................ ................................ ................................ . 13-15 column control register (clmcon) ................................ ................................ .............................. 13-15 character color control register (colbuf) ................................ ................................ ................... 13-17 background color control ................................ ................................ ................................ ..................... 13-18 v-sync blank control register (vsbcon) ................................ ................................ ................... 13-20 v-sync blank and top margin timing diagram ................................ ................................ ............. 13-21 halftone signal control register (htcon) ................................ ................................ ...................... 13-22 osd field control register (osdfld) ................................ ................................ ................................ .. 13-25 osd palette color control ................................ ................................ ................................ ............ 1 3-27 osd space color control register (osdcol) ................................ ................................ ............... 13-31 osd border/fringe function ................................ ................................ ................................ ......... 13-33 osd smooth fucntion ................................ ................................ ................................ ................. 13-35
s3c880a/f880a microcontroller ix table of contents (concluded) chapter 14 analog-to-digital converter overview ................................ ................................ ................................ ................................ ............. 14-1 using a/d pins for standard digital input ................................ ................................ ....................... 14- 2 a/d converter control register (adcon) ................................ ................................ ....................... 14- 2 internal reference voltage levels ................................ ................................ ................................ .. 14- 3 conversion timing ................................ ................................ ................................ ....................... 14- 4 internal a/d conversion procedure ................................ ................................ ................................ 14- 4 chapter 15 electrical data overview ................................ ................................ ................................ ................................ ............. 15-1 chapter 16 mechanical data overview ................................ ................................ ................................ ................................ ............. 16-1 chapter 17 S3F880A overview ................................ ................................ ................................ ................................ ............. 17-1 chapter 18 development tools overview ................................ ................................ ................................ ................................ ............. 18-1 shine ................................ ................................ ................................ ................................ ......... 18-1 sama assembler ................................ ................................ ................................ ........................ 18-1 sasm88 ................................ ................................ ................................ ................................ ..... 18-1 hex2rom ................................ ................................ ................................ ................................ .. 18-1 target boards ................................ ................................ ................................ ............................. 18-2 tb880a target board ................................ ................................ ................................ ................... 18-3

s3c880a/f880a microcontroller xi list of figures figure title page number number 1-1 block diagram ................................ ................................ ................................ .... 1-3 1-2 s3c880a/f880a pin assignment (42-sdip) ................................ .......................... 1-4 1-3 s3c880a/f880a pin assignment (44-qfp) ................................ ........................... 1-5 1-4 pin circuit type 1 (v-sync h-sync, capa) ................................ ........................... 1-8 1-5 pin circuit type 2 (p2.0?p2.7, p0.0?p0.3, pwm0?pwm5, t0, osdht) .................. 1-8 1-6 pin circuit type 3 (p0.4?p0.5, p1.6?p1.7, t0ck) ................................ .................. 1-8 1-7 pin c ircuit type 4 (vblue, vgreen, vred, vblank) ................................ .................... 1-9 1-8 pin circuit type 5 (p1.4?p1.5) ................................ ................................ .............. 1-9 1-9 pin circuit type 6 (p3.0?p3.1, p0.6?p0.7, adc0?adc3) ................................ ........ 1-9 1-10 pin circuit type 7 (p1.0?p1.3, int0?int3) ................................ ............................. 1-10 1-11 pin circuit type 8 (nreset) ................................ ................................ ................ 1-10 2-1 program memory address spaces ................................ ................................ ........ 2-2 2-2 internal register file organization ................................ ................................ ......... 2-4 2-3 rom code option (rcod_opt) ................................ ................................ ........... 2-5 2-4 register page pointer (pp) ................................ ................................ .................. 2-6 2-5 programming tip example for inter-page data operations ................................ ....... 2-7 2-6 set 1, set 2, and prime area register map ................................ ........................... 2-15 2-7 8-byte working register areas (slices) ................................ ................................ . 2-16 2-8 contiguous 16-byte working register block ................................ .......................... 2-17 2-9 non-contiguous 16-byte working register block ................................ ................... 2-18 2-9 16-bit register pairs ................................ ................................ ............................ 2-19 2-10 register file addressing ................................ ................................ ...................... 2-20 2-12 common working register area ................................ ................................ ........... 2-21 2-13 4-bit working register addressing ................................ ................................ ........ 2-23 2-14 4-bit working register addressing example ................................ .......................... 2-23 2-15 8-bit working register addressing ................................ ................................ ........ 2-24 2-16 8-bit working register addressing example ................................ .......................... 2-25 2-17 stack operations ................................ ................................ ................................ 2-26 3-1 register addressing ................................ ................................ ............................ 3-2 3-2 working register addressing ................................ ................................ ............... 3-2 3-3 indirect register addressing to register file ................................ .......................... 3-3 3-4 indirect register addressing to program memory ................................ ................... 3-4 3-5 indirect working register addressing to register file ................................ ............. 3-5 3-6 indirect working register addressing to program or data memory ........................... 3-6 3-7 indexed addressing to register file ................................ ................................ ...... 3-7 3-8 indexed addressing to program or data memory with short offset ........................... 3-8 3-9 indexed addressing to program or data memory ................................ .................... 3-9 3-10 direct addressing for load instructions ................................ ................................ .. 3-10 3-11 direct addressing for call and jump instructions ................................ .................... 3-11 3-12 indirect addressing ................................ ................................ .............................. 3-12 3-13 relative addressing ................................ ................................ ............................. 3-13 3-14 immediate addressing ................................ ................................ ......................... 3-14 4-1 register description format ................................ ................................ ................. 4-5
xii s3c880a/f880a microcontroller list of figures (continued) figure title page number number 5-1 s3c8-series interrupt types ................................ ................................ ................. 5-2 5-2 s3c880a/f880a interrupt structure ................................ ................................ ...... 5-3 5-3 rom vector address area ................................ ................................ ................... 5-4 5-4 interrupt function diagram ................................ ................................ ................... 5-7 5-5 system mode register (sym) ................................ ................................ .............. 5-9 5-6 interrupt mask register (imr) ................................ ................................ ............... 5-10 5-7 interrupt priority register (ipr) ................................ ................................ ............. 5-11 5-8 interrupt request register (irq) ................................ ................................ ........... 5-12 6-1 system flags register (flags) ................................ ................................ ........... 6-6 7-1 main oscillator circuit (external crystal or ceramic resonator) ............................... 7-1 7-2 system clock circuit diagram ................................ ................................ .............. 7-2 7-3 system clock control register (clkcon) ................................ ............................. 7-3 7-4 l-c oscillator circuit for osd ................................ ................................ ............... 7-4 8-1 stop state timing diagram ................................ ................................ ................... 8-7 9-1 port data register format ................................ ................................ .................... 9-2 9-2 port 0 high-byte control register (p0conh) ................................ ......................... 9-3 9-3 port 0 low-byte control register (p0conl) ................................ .......................... 9-3 9-4 port 1 high-byte control register (p1conh) ................................ ......................... 9-4 9-5 port 1 low-byte control register (p1conl) ................................ .......................... 9-4 9-6 port 2 high-byte control register (p2conh) ................................ ......................... 9-5 9-7 port 2 low-byte control register (p2conl) ................................ .......................... 9-5 9-8 port 3 control register (p3con) ................................ ................................ ........... 9-6 10-1 basic timer control register (btcon) ................................ ................................ .. 10-2 10-2 oscillation stabilization time on reset ................................ ............................... 10-4 10-3 oscillation stabilization time on stop mode release ................................ ............ 10-5 10-4 timer 0 control register (t0con) ................................ ................................ ......... 10-6 10-5 timer 0 function diagram (interval timer mode) ................................ ..................... 10-7 10-6 timer 0 function diagram (pwm mod e) ................................ ................................ 10-8 10-7 basic timer and timer 0 block diagram ................................ ................................ 10-9 11-1 timer a block diagram ................................ ................................ ........................ 11-2 11-2 timer a control register (tacon) ................................ ................................ ........ 11-3
s3c880a/f880a microcontroller xiii list of figures (continued) figure title page number number 12-1 pwm control register (pwmcon) ................................ ................................ ....... 12-2 12-2 block diagram for pwm2?pwm5 ................................ ................................ ......... 12-3 12-3 pwm waveforms for pwm2?pwm5 ................................ ................................ ..... 12-5 12-4 pwm clock to pwm2?pwm5 output delays ................................ ........................ 12-6 12-5 block diagram for pwm0 and pwm1 ................................ ................................ .... 12-9 12-6 decision flowchart for pwm0 programming tip ................................ ..................... 12-10 12-7 block diagram for capture a ................................ ................................ ................ 12-12 12-8 decision flowchart (main routine and timer a interrupt) ................................ ......... 12-14 12-9 decision flowchart for capture a interrupt ................................ ............................. 12-15 13-1 on-screen display function block diagram ................................ ........................... 13-3 13-2 on-screen display video ram data organization ................................ .................. 13-4 13-3 osd display control register (dspcon) ................................ .............................. 13-6 13-4 osd character size control register (chacon) ................................ ................... 13-8 13-5 osd character sizing dimensions ................................ ................................ ........ 13-9 13-6 osd fade control register (fadecon) ................................ ............................... 13-10 13-7 line and row addressing conventions when rowcon.2-.0 = "100" ........................ 13-11 13-8 osd fade function example: fade after ................................ .............................. 13-12 13-9 osd fade function example: fade before ................................ ............................ 13-13 13-10 252-byte on-screen character display map (decimal) ................................ ........... 13-14 13-11 252-byte on-screen character display map (hexadecimal) ................................ .... 13-14 13-12 osd row control register (rowcon) ................................ ................................ . 13-15 13-13 osd column control register (clmcon) ................................ .............................. 13-15 13-14 osd display formatting and spacing conventions ................................ ................. 13-16 13-15 osd character color buffer register (colbuf) ................................ ..................... 13-17 13-16 background color display conventions ................................ ................................ .. 13-18 13-17 osd background color cont rol register (colcon) ................................ ............... 13-19 13-18 v-sync blank control register (vsbcon) ................................ ............................. 13-20 13-19 v-sync blank and top margin timing diagram ................................ ....................... 13-21 13-20 halftone signal control register (htcon) ................................ .............................. 13-23 13-21 halftone or character backgound signal output ................................ ..................... 13-24 13-22 osd field control register (osdfld) ................................ ................................ .. 13-25 13-23 field detect in before v-sync ................................ ................................ ............... 13-26 13-24 field detect in after v-sync ................................ ................................ .................. 13-26 13-25 osd palette color mode register r1 (osdpltr1) ................................ ................ 13-27 13-26 osd palette color mode register r2 (osdpltr2) ................................ ................ 13-28 13-27 osd palette co lor mode register g1 (osdpltg1) ................................ ................ 13-29 13-28 osd palette color mode register g2 (osdpltg2) ................................ ................ 13-29 13-29 osd palette color mode register b1 (osdpltb1) ................................ ................ 13-30 13-30 osd palette color mode register b2 (osdpltb2) ................................ ................ 13-30 13-31 osd space color control register (osdcol) ................................ ....................... 13-32 13-32 osd fringe/border control register 1 (osdfrg1) ................................ ................. 13-34 13-33 osd fringe/border control register 2 (osdfrg2) ................................ ................. 13-34
xiv s3c880a/f880a microcontroller list of figures (concluded) figure title page number number 13-34 osd smooth control register 1 (osdsmh1) ................................ ........................ 13-35 13-35 osd smoo th control register 2 (osdsmh2) ................................ ........................ 13-36 13-36 smoothing/fringing/priority of smoothing and fringing ................................ ............ 13-36 13-37 decision flowchart for row interrupt function programming tip ............................... 13-37 13-38 decision flowchart for fade function programming tip ................................ .......... 13-40 14-1 a/d converter control register (adcon) ................................ ............................... 14-2 14-2 a/d converter circuit diagram ................................ ................................ .............. 14-3 14-3 a/d converter data register (addatah/l) ................................ ............................ 14-3 14-4 s3c880a/f880a a/d converter timing diagram ................................ ..................... 14-4 14-5 recommended a/d converter circuit for highest absolute accuracy ........................ 14-5 15-1 input timing measurement points for t nf1 and t nf2 ................................ ................. 15-5 15-2 stop mode release timing when initiated by a nreset ................................ ........ 15-5 15-3 clock timing measurement points for x in ................................ .............................. 15-6 16-1 42-pin sdip package dimensions (42-sdip-600) ................................ ................... 16-1 16-2 44-pin qfp package dimensions (44-qfp-1010b) ................................ ................ 16-2 17-1 descriptions of pins used to read/write the flash rom (S3F880A) ........................ 17-2 18-1 smds product configuration (smds2+) ................................ ................................ 18-2 18-2 tb880a target board configuration ................................ ................................ ....... 18-3 18-3 50-pin dip connector j101 for tb880a ................................ ................................ .. 18-7 18-4 s3c8 80a/f880a probe adapter for 42-sdip package ................................ ............ 18-7
s3c880a/f880a microcontroller xv list of tables table title page number number 1-1 s3c880a/f880a pin descriptions ................................ ................................ ......... 1-5 2-1 program rom and character rom area by the font figure ................................ .... 2-3 2-2 register type summary ................................ ................................ ....................... 2-3 4-1 set 1 registers ................................ ................................ ................................ ... 4-2 4-2 set 1, bank 0 registers ................................ ................................ ....................... 4-2 4-3 set 1, bank 1 registers ................................ ................................ ....................... 4-4 5-1 s3c880a/f880a interrupt vectors ................................ ................................ ........ 5-5 5-2 interrupt control register overview ................................ ................................ ........ 5-6 5-3 interrupt source control registers ................................ ................................ ......... 5-8 6-1 instruction group summary ................................ ................................ .................. 6-2 6-2 flag notation con ventions ................................ ................................ .................... 6-8 6-3 instruction set symbols ................................ ................................ ....................... 6-8 6-4 instruction notation conventions ................................ ................................ ........... 6-9 6-5 opcode quick reference ................................ ................................ ..................... 6-10 6-6 condition codes ................................ ................................ ................................ .. 6-12 8-1 set 1 register values after a reset ................................ ................................ ...... 8-2 8-2 set 1, bank 0 register values after a reset ................................ .......................... 8-3 8-3 page 1 video ram register values after a reset ................................ .................. 8-4 9-1 s3c880a/f880a port configuration overview ................................ ......................... 9-1 9-2 port data register summary ................................ ................................ ................ 9-2 12-1 pwm0 and pwm1 control and data registers ................................ ...................... 12-8 12-2 pwm output "stretch" values for extension registers pwm0ex and p wm1ex ....... 12-8 13-1 osd function block summary ................................ ................................ ............. 13-1 15-1 absolute maximum ratings ................................ ................................ .................. 15-2 15-2 d.c. electrical characteristics ................................ ................................ .............. 15-2 15-3 input/output capacitance ................................ ................................ ..................... 15-4 15-4 a.c. electrical characteristics ................................ ................................ .............. 15-4 15-5 analog r,g,b output ................................ ................................ ........................... 15-4 15-6 data retention supply voltage in stop mode ................................ ......................... 15-5 15-7 main oscillator and l-c oscillator frequency ................................ ......................... 15-6 15-8 main oscillator clock stabilization time ................................ ................................ 15-7 15-9 a/d converter electrical characteristics ................................ ................................ 15-7 17-1 power selection settings for tb880a ................................ ................................ .... 17-4 17-2 the smds 2 + tool selection setting ................................ ................................ .... 17-5 17-3 osd font rom selection setting ................................ ................................ ......... 17-5 17-4 using single header pins as the input path for external trigger sources .................. 17-6

s3c880a/f880a microcontroller xvii list of programming tips description page number chapter 2: address spaces data operations between register pages ................................ ................................ ......................... 2-7 examples of inter-page data transfer operations ................................ ................................ ............... 2-8 setting the register pointers ................................ ................................ ................................ ............ 2-17 using the rps to calculate the sum of a series of registers ................................ .............................. 2-18 addressing the common working register area ................................ ................................ ................ 2-22 chapter 5: interrupt structure programming level irq0 as a fast interrupt ................................ ................................ ...................... 5-18 chapter 12: pwm and capture programming pwm0 to sample specifications ................................ ................................ .................. 12-10 programming the capture module to sample specifications ................................ ................................ 12-16 chapter 13: on-screen display (osd) row interrupt function ................................ ................................ ................................ ..................... 13-37 writing character code and color data to the osd video ram ................................ ........................... 13-39 osd fade function; line and row counters ................................ ................................ ..................... 13-39 manipulating osd character colors; halftone function ................................ ................................ ....... 13-43 osd character size, background color, and display position ................................ ............................. 13-45 helpful hints about colbuf and osd character code 0 ................................ ................................ ... 13-45 chapter 14: analog-to-digital converter configuring a/d converter ................................ ................................ ................................ ................. 14-5

s3c880a/f880a microcontroller xix list of register descriptions register full register name page identifier number adcon a/d converter control register ................................ ................................ ............. 4-6 btcon basic timer control register ................................ ................................ ................ 4-7 chacon osd character size control register ................................ ................................ .... 4-8 clkcon system clock control register ................................ ................................ ............. 4-9 clmcon osd column control register ................................ ................................ .............. 4-10 colbuf osd character color buffer ................................ ................................ .................. 4-11 colcon osd background color control register ................................ ................................ 4-12 dspcon on-screen dis play control register ................................ ................................ ...... 4-13 emt external memory timing register ................................ ................................ ......... 4-14 fadecon osd fade control register ................................ ................................ .................. 4-15 flags system flag register ................................ ................................ .......................... 4-16 hcon hdlc control register ................................ ................................ ......................... 4-17 imr interrupt mask register ................................ ................................ ....................... 4-18 iph instruction pointer (high byte) ................................ ................................ .............. 4-19 ipl instruction pointer (low byte) ................................ ................................ ............... 4-19 ipr interrupt priority register ................................ ................................ ...................... 4-20 irq interrupt request register ................................ ................................ .................... 4-21 osdcol osd space color control register ................................ ................................ ........ 4-22 osdfld osd field control register ................................ ................................ .................. 4-23 osdfrg1 osd fringe/border control register 1 ................................ ................................ ... 4-24 osdfrg2 osd fringe /border control register 2 ................................ ................................ ... 4-25 osdpltb1 osd palette color mode register b1 ................................ ................................ .... 4-26 osdpltb2 osd palette color mode register b2 ................................ ................................ .... 4-27 osdpltg1 osd palette color mode register g1 ................................ ................................ .... 4-28 osdpltg2 osd palette color mode register g2 ................................ ................................ .... 4-29 osdpltr1 osd palette color mode register r1 ................................ ................................ .... 4-30 osdpltr2 osd palette color mode register r2 ................................ ................................ .... 4-31
xx s3c880a/f880a microcontroller list of register descriptions (continued) register full register name page identifier number osdsmh1 osd smooth control register 1 ................................ ................................ ........... 4-32 osdsmh2 osd smooth control register 2 ................................ ................................ ........... 4-33 p0conh port 0 control register (high byte) ................................ ................................ ....... 4-34 p0conl port 0 control register (low byte) ................................ ................................ ........ 4-35 p1conh port 1 control register (high byte) ................................ ................................ ....... 4-36 p1conl port 1 control register (low byte) ................................ ................................ ........ 4-37 p2conh port 2 control register (high byte) ................................ ................................ ....... 4-38 p2conl port 2 control register (low byte) ................................ ................................ ........ 4-39 p3conh port 3 control register (high byte) ................................ ................................ ....... 4-40 pp register page pointer ................................ ................................ .......................... 4-41 pwmcon pwm control register ................................ ................................ ......................... 4-42 rowcon osd row position control register ................................ ................................ ...... 4-43 rp0 register pointer 0 ................................ ................................ ................................ 4-44 rp1 register pointer 1 ................................ ................................ ................................ 4-44 sph stack pointer (high byte) ................................ ................................ ..................... 4-45 spl stack pointer (low byte) ................................ ................................ ..................... 4-45 stcon stop control register ................................ ................................ ........................... 4-46 sym system mode register ................................ ................................ ........................ 4-47 tacon 8-bit timer a control register ................................ ................................ .............. 4-48 t0con timer 0 control register ................................ ................................ ....................... 4-49 vsbcon v-sync blank control register ................................ ................................ ............. 4-50
s3c880a/f880a microcontroller xxi list of instruction descriptions instruction full register name page mnemonic number adc add with carry ................................ ................................ ................................ .... 6-14 add add ................................ ................................ ................................ .................... 6-15 and logical and ................................ ................................ ................................ ........ 6-16 band bit and ................................ ................................ ................................ .............. 6-17 bcp bit compare ................................ ................................ ................................ ........ 6-18 bitc bit complement ................................ ................................ ................................ .. 6-19 bitr bit reset ................................ ................................ ................................ ............ 6-20 bits bit set ................................ ................................ ................................ ................ 6-21 bor bit or ................................ ................................ ................................ ................ 6-22 btjrf bit test, jump relative on false ................................ ................................ ........... 6-23 btjrt bit test, jump relative on true ................................ ................................ ............. 6-24 bxor bit xor ................................ ................................ ................................ .............. 6-25 call call procedure ................................ ................................ ................................ .... 6-26 ccf complement carry flag ................................ ................................ ....................... 6-27 clr clear ................................ ................................ ................................ .................. 6-28 com complement ................................ ................................ ................................ ....... 6-29 cp compare ................................ ................................ ................................ ............. 6-30 cpije compare, increment, and jump on equal ................................ ............................... 6-31 cpijne compare, increment, and jump on non-equal ................................ ........................ 6-32 da decimal adjust ................................ ................................ ................................ .... 6-33 dec decrement ................................ ................................ ................................ .......... 6-35 decw decrement word ................................ ................................ ................................ . 6-36 di disable interrupts ................................ ................................ ................................ 6-37 div divide (unsigned) ................................ ................................ ................................ . 6-38 djnz decrement and jump if non-zero ................................ ................................ .......... 6-39 ei enable interrupts ................................ ................................ ................................ . 6-40 enter enter ................................ ................................ ................................ .................. 6-41 exit exit ................................ ................................ ................................ .................... 6-42 idle idle operation ................................ ................................ ................................ ...... 6-43 inc increment ................................ ................................ ................................ ........... 6-44 incw increment word ................................ ................................ ................................ ... 6-45 iret interrupt return ................................ ................................ ................................ ... 6-46 jp jump ................................ ................................ ................................ .................. 6-47 jr jump relative ................................ ................................ ................................ ...... 6-48 ld load ................................ ................................ ................................ ................... 6-49 ldb load bit ................................ ................................ ................................ .............. 6-51
xxii s3c880a/f880a microcontroller list of instruction descriptions (continued) instruction full register name page mnemonic number ldc/lde load memory ................................ ................................ ................................ ...... 6-52 ldcd/lded load memory and decrement ................................ ................................ ............... 6-54 ldci/ldei load memory and increment ................................ ................................ ................ 6-55 ldcpd/ldepd load memory with pre-decrement ................................ ................................ ........ 6-56 ldcpi/ldepi load memory with pre-increment ................................ ................................ .......... 6-57 ldw l oad word ................................ ................................ ................................ .......... 6-58 mult multiply (unsigned) ................................ ................................ .............................. 6-59 next next ................................ ................................ ................................ ................... 6-60 nop no operation ................................ ................................ ................................ ....... 6-61 or logical or ................................ ................................ ................................ .......... 6-62 pop pop from stack ................................ ................................ ................................ ... 6-63 popud pop user stack (decrementing) ................................ ................................ ............ 6-64 popui pop user stack (incrementing) ................................ ................................ ............. 6-65 push push to stack ................................ ................................ ................................ ..... 6-66 pushud push user stack (decrementing) ................................ ................................ .......... 6-67 pushui push user stack (incrementing) ................................ ................................ ........... 6-68 rcf reset carry flag ................................ ................................ ................................ . 6-69 ret return ................................ ................................ ................................ ................ 6-70 rl rotate left ................................ ................................ ................................ .......... 6-71 rlc rotate left through carry ................................ ................................ ..................... 6-72 rr rotate right ................................ ................................ ................................ ........ 6-73 rrc rotate right through carry ................................ ................................ ................... 6-74 sb0 select bank 0 ................................ ................................ ................................ ..... 6-75 sb1 select bank 1 ................................ ................................ ................................ ..... 6-76 sbc subtract with carry ................................ ................................ .............................. 6-77 scf set carry flag ................................ ................................ ................................ ..... 6-78 sra shift right arithmetic ................................ ................................ ........................... 6-79 srp/srp0/srp1 set register pointer ................................ ................................ ............................ 6-80 stop stop operation ................................ ................................ ................................ .... 6-81 sub subtract ................................ ................................ ................................ ............. 6-82 swap swap nibbles ................................ ................................ ................................ ...... 6-83 tcm test complement under mask ................................ ................................ .............. 6-84 tm test under mask ................................ ................................ ................................ . 6-85 wfi wait for interrupt ................................ ................................ ................................ .. 6-86 xor logical exclusive or ................................ ................................ ........................... 6-87
s3c880a/f880a produ ct overview 1- 1 1 product overview overview the s3c880a/f880a microcontroller has 48-kbytes of on-chip program memory. this chips have a 336-byte general- purpose internal register file. the interrupt structure has 9 interrupt sources with 9 interrupt vectors. the cpu recognizes seven interrupt priority levels. using a modular design approach, the following peripherals were integrated with the sam88lp core to make the s3c880a/f880a microcontrollers suitable for use in color television and other types of screen display applications: ? four programmable i/o ports (26 pins total: 16 general-purpose i/o pins; 10 n-channel, open-drain output pins) ? four channel a/d converter (8-bit resolution) ? two 14-b it pwm output and four 8-bit pwm output. ? basic timer (bt) with watchdog timer function ? one 8-bit general-purpose timer/counter (t0) with interval timer mode and pwm output mode ? one 8-bit timer/counters (ta) with prescalers and interval timer mode ? on-screen display (osd) with a wide range of programmable features, including halftone control signal output the s3c880a/f880a is available in a versatile 42-pin sdip, 44-pin qfp package.
product overview s3 c880a/f880a 1- 2 features cpu ? sam88lp cpu core memory ? 48-k byte internal program and osd font memory ? 336-byte general-purpose register area instruction set ? 78 instructions ? idle and stop instructions added for power-down modes instruction execution time ? 750 ns (minimum) with an 8-mhz cpu clock interrupts ? 9 interrupt sources with 9 vectors ? 7 interrupt levels ? fast interrupt processing for select levels general i/o ? four i/o ports (26 pins total) ? six open-drain pins for up to 6-volt loads ? four open-drain pins for up to 5-volt loads 8-bit basic timer ? three select able internal clock frequencies ? watchdog or oscillation stabilization function timer/counters ? one 8-bit timer/counter (t0) with three internal clocks or an external clock, and two operating modes; interval mode or pwm mode ? one general-purpose 8-bit timer/counters with interval timer (timer a) a/d converter ? four analog input pins ? 8-bit resolution ? 25 us conversion time (8-mhz cpu clock) pulse width modulation module ? 14-bit pwm with 2-channel output ? 8-bit pwm with 4-channel out put ? pwm counter and data capture input pin ? frequency: 5.859 khz to 23.437 khz with a 6-mhz cpu clock on-screen display (osd) ? video ram: 252 14 bits ? character generator rom: variable size max:1024 18 16 bits min: default 2 font reserved. (1024 display characters: fixed: 2, variable: 1022) ? 252 display positions (12 rows 21 columns) ? 16-dot 18-dot character resolution ? 16 different character sizes ? 64 character colors ? fade in/out ? 64 colors for character and fram e background ? halftone control signal output; select able for individual characters ? synchronous polarity selector for h-sync and v -sync input ? bordering function ? smoothing function ? fringing function oscillator frequency ? 5-mhz to 8-mhz external crystal oscillator (when osd block active) ? maximum 8-mhz cpu clock operating temperature range ? - 20 c to + 85 c operating voltage range ? 4.5 v to 5.5 v package type ? 42-pin sdip, 44-pin qfp
s3c880a/f880a produ ct overview 1- 3 block diagram main osc l-c osc port 0 p0.0-p0.7 port i/o and interrupt control 48-kbyte rom 336-byte register file sam88lp cpu port 1 sam88 bus x out x in osc out osc in nreset p1.0-p1.7 int0-int3 test timers a capa port 2 p2.0-p2.7 port 3 p3.0-p3.1 pwm block pwm counter and data capture 14-bit pwm 8-bit pwm timer 0 capa t0 8-bit adc adc0 adc1 adc2 adc3 on- screen display h-sync v-sync vred vgreen vblue vblank osdht pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 figure 1-1. block diagram
product overview s3 c880a/f880a 1- 4 pin assignments pwm0/p2.5 pwm1/p2.1 pwm2/p2.2 pwm3/p2.3 pwm4/p2.4 pwm5/p2.0 t0/p2.6 t0ck/p1.7 adc0/p3.0 adc1/p3.1 adc2/p0.6 adc3/p0.7 test int0/p1.0 int1/p1.1 int2/p1.2 int3/p1.3 p1.4 p1.5 p1.6 osdht/p2.7 s3c880a S3F880A (42-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p0.0 p0.1 p0.2 p0.3 p0.4 v ss cap.a p0.5 v dd nreset x out x in v ss1 osc out osc in v-sync h-sync vblank vred vgreen vblue 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1-2. s3c880a/f880a pin assignment (42-sdip)
s3c880a/f880a produ ct overview 1- 5 p1.3/int3 p1.4 p1.5 p1.6 p2.7/osdht vblue vgreen vred vblank h-sync v-sync nc cap.a p0.5 v dd nreset x out x in v ss1 nc osc out osc in p2.4/pwm4 p2.3/pwm3 p2.2/pwm2 p2.1/pwm1 p2.5/pwm0 p0.0 p0.1 p0.2 p0.3 p0.4 v ss p2.0/pwm5 p2.6/t0 p1.7/t0clk p3.0/adc0 p3.1/adc1 p0.6/adc2 p0.7/adc3 test p1.0/int0 p1.1/int1 p1.2/int2 s3c880a S3F880A (44-qfp) 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 figure 1-3. s3c880a/f880a pin assignment (44-qfp)
product overview s3 c880a/f880a 1- 6 pin descriptions table 1-1. s3c880a/f880a pin descriptions pin name pin type pin description circuit type pin numbers share pins p0.0?p0.3 i/o general i/o port (4-bit), configurable for digital input or n-channel open-drain, push-pull output. pins can withstand up to 5-volt loads. 2 39?42 (39?36) (see pin description) p0.4?p0.5 general i/o port (2-bit), configurable for digital input or push-pull output. 3 38, 35 (35, 31) p0.6?p0.7 general i/o port (2-bit), configurable for digital input or n-channel open-drain output. p0.6-p0.7 can withstand up to 5-volt loads. multiplexed for alternative use as external inputs adc2-adc3. 6 11?12 (6?7) adc2?adc3 p1.0?p1.3 i/o general i/o port (4-bit), configurable for digital input or n-channel open-drain output. p1.0-p1.3 can withstand up to 6-volt loads. multiplexed for alternative use as external interrupt inputs int0-int3 7 14?17 (9?11) int0 ?int3 p1.4?p1.5 general i/o port (2-bit). configurable for digital input or n-channel open-drain output. p1.4-p1.5 can withstand up to 6-volt loads. high current port (10ma). 5 18?19 (13?14) p1.6?p1.7 general i/o port (2-bit). configurable for digital input or push-pull output. each pin has an alternative function. p1.7: t0ck (timer 0 clock input) 3 20, 8 (15, 3) t0ck p2.0?p2.7 i/o general i/o port (8-bit). input/output mode or n- channel open-drain, push-pull output mode is software configurable. pins can withstand up to 5- volt loads. each pin has an alternative function. p2.0: pwm5 (8-bit pwm output) p2.1: pwm1 (14-bit pwm output) p2.2: pwm2 (8-bit pwm output) p2.3: pwm3 (8-bit pwm output) p2.4: pwm4 (8-bit pwm output) p2.5: pwm0 (14-bit pwm output) p2.6: t0 (timer 0 pwm and interval output) p2.7: osdht (halftone signal output) 2 1?7, 21 (1, 41?44, 40, 2, 16) pwm0?pwm5 t0, osdht p3.0?p3.1 i/o general i/o port (2-bit), configurable for digital input or n-channel open-drain output. p3.0-p3.1 can withstand up to 5-volt loads. multiplexed for alternative use as external inputs adc0-adc1. 6 9?10 (4?5) adc0?adc1 note: parentheses indicate pin number for 44-qfp package.
s3c880a/f880a produ ct overview 1- 7 table 1-1. s3c880a/f880a pin descriptions (continued) pin name pin type pin description circuit type pin numbers share pins pwm0 o output pin for 14-bit pwm circuit 1 1 (40) p2.5 pwm1 o output pin for 14-bit pwm circuit 2 2 (41) p2.1 pwm2?pwm4 o output pin for 8-bit pwm circuit 2 3?5 (42?44) p2.2?p2.4 pwm5 o output pin for 8-bit pwm circuit 2 6 (1) p2.0 adc0?adc1 i analog inputs for 8-bit a/d converter 6 9,10 (4,5) p3.0?p3.1 adc2?adc3 i analog inputs for 8-bit a/d converter 6 11,12 (6,7) p0.6?p0.7 int0?int3 i external interrupt input pins 7 14?17 (9?11) p1.0?p1.3 t0 o timer 0 output (interval, pwm) 2 7 (2) p2.6 t0ck i timer 0 clock input 3 8 (3) p1.7 osdht o halftone control signal output for osd 2 21 (16) p2.7 vblue, vgreen vred o digital blue, green and red signal outputs for osd 4 22?24 (17?19) ? vblank o digital video blank signal outputs for osd 4 25 (20) ? h-sync, v-sync i h-sync, v-sync input for osd 1 26, 27 (21,22) ? osc in , osc out i, o l-c oscillator pins for osd clock frequency generation ? 28, 29 (23,24) ? x in , x out i, o system clock pins ? 31, 32 (27,28) ? nreset i system reset input pin 8 33 (29) ? test ? test pin (must be connected to v ss ). factory test mode is activated when 12 v is applied. ? 13 (8) ? v dd , v ss ? power supply pins ? 30, 34, 37 (26,30,34) ? capa i input for capture a module 1 36 (32) ? note: parentheses indicate pin number for 44-qfp package.
product overview s3 c880a/f880a 1- 8 pin circuits input noise filter figure 1-4. pin circuit type 1 (v-sync h-sync, capa) v dd data output disable input i/o open-drain figure 1-5. pin circuit type 2 (p2.0?p2.7, p0.0?p0.3, pwm0?pwm5, t0, osdht) v dd data input output v ss figure 1-6. pin circuit type 3 (p0.4?p0.5, p1.6?p1.7, t0ck)
s3c880a/f880a produ ct overview 1- 9 v dd data output v ss figure 1-7. pin circuit type 4 (vblue, vgreen, vred, vblank) data input i/o v ss figure 1-8. pin circuit type 5 (p1.4?p1.5) data input i/o v ss a/d in note: circuit type 6 can withstand up to 5 v loads. figure 1-9. pin circuit type 6 (p3.0?p3.1, p0.6?p0.7, adc0?adc3)
product overview s3 c880a/f880a 1- 10 data input i/o int note: circuit type 7 can withstand up to 6 v loads. noise filter v ss figure 1-10. pin circuit type 7 (p1.0?p1.3, int0?int3) noise filter v dd 250 k w figure 1-11. pin circuit type 8 (nreset)
s3c880a/f880a address spaces 2 - 1 2 address spaces overview the s3c880a/f880a microcontroller ha s two kinds of address space: ? internal program memory (rom) ? internal register file the s3c880a/f880a ha s an on-chip 48- k byte mask- programmable. there are 336 general-purpose 8-bit data registers in the register file. seventeen 8-bit registers are used for cpu and system control. to support peripheral, i/o, and clock functions, there are 33 control registers and 16 data registers. in addition, there is a 2 52 4 -bit area for on-screen display (osd) video ram.
address spaces s3c880a/f880a 2 - 2 program memory (rom) the s3c880a/f880a ha s a 48- k byte mask-programmable program memory . program memory stores program code s , table data or osd font codes . as shown in figure 2 - 1, the first 256 bytes of the rom (0h ? 0ffh) are reserved for interrupt vector addresses. unused locations in this range can be used as normal program memory. if the vector address area is used to store normal program data, care must be taken to avoid overwriting vector addresses stored in these locations. the rom address at which program execution starts after a nreset is 0100h. interrupt vector area program memory and character generator memory 0h bfffh rom code option area 3ch 40h 100h figure 2 - 1. program memory address spaces
s3c880a/f880a address spaces 2 - 3 table 2 - 1. program rom and character rom area by the font figure font rom program rom character rom 0 rom size 48-kbyte 0-kbyte rom address 0-bfffh 0 256 rom size 39-kbyte 9-kbyte rom address 0-9bffh 9c00h-bfffh 384 rom size 34.5-kbyte 13.5-kbyte rom address 0-89ffh 8a00h-bfffh 512 rom size 30-kbyte 18-kbyte rom address 0-77ffh 7800h-bfffh 640 rom size 25.5-kbyte 22.5-kbyte rom address 0-65ffh 6600h-bfffh 768 rom size 21-kbyte 27-kbyte rom address 0-53ffh 5400h-bfffh 1024 rom size 12-kbyte 36-kbyte rom address 0-2fffh 3000h-bfffh register architecture the upper 64 bytes of the s3c880a/f880a internal register file is logi cally expanded into two 64-byte areas, called set 1 and set 2 . the upper 32-byte area of set 1 is divided into two register banks, called bank 0 and bank 1 . in addition, two register pages are implemented, called page 0 and page 1 . the total addressable register space is thereby expanded from 256 bytes to 654 bytes. the extension of the physical register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, sb0 and sb1, and the register page pointer (pp). specific register types and the area (in bytes) that they occupy in the register file are summarized in table 2 - 1. table 2 -2 . register type summary register type number of bytes general-purpose registers (including the 16-byte working register common area) 336 cpu and system control registers 17 peripheral, i/o, and clock control/data registers 49 on-screen display (osd) video ram 252 total addressable bytes 654
address spaces s3c880a/f880a 2 - 4 bank 1 ffh e0h d0h c0h set 2 general purpose registers (indirect address mode) c0h 00h prime data registers (all address mode) page 0 ffh bfh set 2 osd registers (indirect address mode) c0h 00h osd registers (all address mode) page 1 ffh bfh 40h 00h ffh 3fh prime data register area (all address mode) page 2 dfh bank 0 cfh ffh e0h set 1 fbh not used system registers data register area display register area (video ram) working registers system and peripheral control registers figure 2 - 2. internal register file organization
s3c880a/f880a address spaces 2 - 5 rom code option (rcod_opt) the address of rcod_opt, from 3ch to 3fh, are rom code option area. by setting the value of rcod_opt, s3c880a/f880a operates optionally. but in s3c880a/f880a, the rom code option is not available. so rcod_opt area can be used as the normal rom area in s3c880a/f880a. lsb msb not used .7 .6 .5 .4 .3 .2 .1 .0 rom address: 3dh lsb msb not used .7 .6 .5 .4 .3 .2 .1 .0 rom address: 3fh lsb msb rom address: 3eh not used lsb msb rom_code option (rcod_opt) rom address: 3ch not used .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 figure 2-3. rom code option (rcod_opt)
address spaces s3c880a/f880a 2 - 6 register page pointer (pp) the sam8 8lp architecture supports the logical expansion of the physical 256-byte register file in up to 16 separately addressable register pages. page addressing is controlled by the register page pointer, pp, dfh. only two pages are implemented in the s3c880a/f880a microcontrollers: p age 0 and page 2 (00h?3fh) are used as general-purpose register space and page 1 contains a 2 52 4 -bit area for the on-screen display (osd) video rom. as shown in figure 2 - 3, when the upper nibble of the pp register is '0000b', the selected destination address is located on page 0. when the upper nibble value is '0001b', page 1 is the selected destination. the lower nibble of the page pointer controls the source register page destination addressing: when the lower nibble is '0000b', page 0 is the selected source register page; when the lower nibble is '0001b', page 1 is the source register page. after a reset, the page pointer's source value ( the lower nibble) and the destination value ( the upper nibble) are always '0000b', automatically selecting page 0 as both the source and the destination. to select page 1 as the source or destination register page, you must modify the register page pointer values accordingly. because only page 0 , page 1 and page 2 are used in the s3c880a/f880a implementation, only pointer values '0000b' , ?0001b? and ?0010b? ' are used. register page pointer (pp) dfh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb destination register page seleciton bits: 0 0 0 0 b 0 0 0 1 b 0 0 1 0 b 1 1 1 1 b destination: page 0 destination: page 1 destinaton: page 2 not used for the S3F880A not used for the S3F880A . . . . . . source register page seleciton bits: 0 0 0 0 b 0 0 0 1 b 0 0 1 0 b 1 1 1 1 b destination: page 0 destination: page 1 destination: page 2 not used for the S3F880A not used for the S3F880A . . . . . . figure 2 -4 . register page pointer (pp)
s3c880a/f880a address spaces 2 - 7 f programming tip ? data operations between register pages ld pp,#10h ; destination register page 1, source register page 0 ld 20h,45h ; register 20h in page 1 ? content of the register 45h ; in page 0 ? ? ? add 30h,40h ; register 30h in page 1 ? content of 30h in page 1 ; plus (+) the content of 40h in page 0 page 1 20h 30h page 0 40h 45h + figure 2 -5 . programming tip example for inter-page data operations effect of different instructions for inter-page data operations the source and the destination page s for data operations between pages differ, depending on which instruction you use. the following programming tip, "examples of inter-page data transfer operations," provides you with a detailed list of various case.
address spaces s3c880a/f880a 2 - 8 f programming tip ? examples of inter-page data transfer operations example 1. a) adc r1,r0 ; r0 ? source page ; r1 ? destination page b) adc r4,@r2 ; r2, 40h ? source page r2 contains 40h ; r4 ? destination page c) adc r0,#0aah ; r0 ? destination page d) adc 40h,42h ; 42h ? source page ; 40h ? destination page e) adc 40h,@42h ; 42h, 60h ? source page 42h contains 60h ; 40h ? destination page f) adc 40h,#02h ; 40h ? destination page note : the above examples also apply to the instructions add, sub, and, or, and xor. example 2. a) band r0,40h.7 ; 40h ? source page ; r0 ? destination page b) band 40h.7,r0 ; r0 ? source page ; 40h ? destination page note : the above examples also apply to the instructions bor, bxor, and ldb. example 3. a) bcp r3,44h.7 ; 44h ? source page ; r3 ? destination page example 4. a) bitc r3.7 ; r3 ? destination page note : the above examples also apply to the instructions bitr and bits.
s3c880a/f880a address spaces 2 - 9 f programming tip ? examples of inter-page data transfer operations (continued) example 5. a) btjrf skip,r6.7 ; r6 ? source page note : the above example also applies to the instructions btjrt. example 6. a) call @60h ; 60h, 61h ? source page example 7. a) clr 30h ; 30h ? destination page b ) clr @44h ; 44h ? source page 44h contains 40h ; 40h ? destination page note : the above examples also apply to the instructions rl, rlc, and sra. example 8. a) com 03h ; 03h ? destination page b) com @44h ; 44h ? source page 44h contains 40h ; 40h ? destination page note : the above examples also apply to the instructions dec, inc, rr, and rrc. example 9. a) cp r1,r0 ; r0 ? source page ; r1 ? destination page b) cp r2,@r4 ; r4, 40h ? source page r4 contains 40h ; r2 ? destinati on page c) cp 40h,42h ; 42h ? source page ; 40h ? destination page d) cp 40h,@42h ; 42h, 44h ? source page 42h contains 44h ; 40h ? destination page e) cp 20h,#0aah ; 20h ? destination page note : the above examples also apply to the instructions tcm and tm.
address spaces s3c880a/f880a 2 - 10 f programming tip ? examples of inter-page data transfer operations (continued) example 10. a) cpije r3,@r5,skip ; r5, 40h ? source page r5 contains 40h ; r3 ? destination page note : the above example also applies to the instruction cpijne. example 11. a) da 00h ; 00h ? source page b) da @02h ; 02h ? source page 02h contains 40h ; 40h ? destination page example 12. a) decw 60h ; 60h, 61h ? destination page b) decw @00h ; 00h, 01h ? source page 00h contains 48h ; 48h, 49h ? destination page 01h contains 49h note : the above example also applies to the instru ction incw. example 13. a) div 60h,40h ; 40h ? source page ; 60h, 61h ? destination page b) div 60h,@20h ; 20h, 40h ? source page 20h contains 40h ; 60h, 61h ? destination page c) div 60h,#03h ; 60h, 61h ? destination page note : the above example also applies to the instruction incw. example 14. a) djnz r6,loop ; r6 ? destination page note: incase pp = 10h, 11h, this instruction is not valid. example 15. a) jp @60h ; 60h, 61h ? source page
s3c880a/f880a address spaces 2 - 11 f programming tip ? examples of inter-page data transfer operations (continued) example 16. a) ld r0,#0aah ; r0 ? destination page b) ld r0,40h ; 40h ? source page ; r0 ? destination page c) ld 40h,r0 ; r0 ? source page ; 40h ? destination page d) ld r0,@r2 ; r2, 50h ? source page r2 contains 50h ; r0 ? destination page e) ld @r4,r2 ; r4, r2 ? source page r4 contains 40h ; 40h ? destination page f) ld 40h,41h ; 41h ? source page ; 40h ? destination page g) ld 40h,@42h ; 42h, 44h ? source page 42h contains 44h ; 40h ? destination page h) ld 45h,#02h ; 45h ? destination page i) ld @40h,#02h ; 40h ? source page 40h contains 44h ; 44h ? destination page j) ld @40h,42h ; 40h, 42h ? source page 40h contains 44h ; 44h ? destination page k) ld r5,#04h(r0) ; r0, 04h(2 + offset) ? source page r0 contains 02h ; r5 ? destination page l) ld #04h(r0),r1 ; r0, r1 ? source page r0 contains 02h ; 04h ? destination page
address spaces s3c880a/f880a 2 - 12 f programming tip ? examples of inter-page data transfer operations (continued) example 17 . a) ldc r0,@rr6 ; r6, r7 ? source page ; r0 ? destination page b) ldc @rr6,r2 ; r6, r7, r2 ? source page rr6 contains an external memory address c) ldc r0,#01h(rr6) ; r6, r7 ? source page ; r0 ? destination page d) ldc #01h(rr6),r0 ; r0, r6, r7 ? source page e) ldc r0,#1000h(rr6) ; r6, r7 ? source page ; r0 ? destination page f) ldc #1000h(rr6),r0 ; r0, r6, r7 ? source page example 18 . a) ldcd r0,@rr6 ; r6, r7 ? source page ; r0 ? destination page b) ldcpd @rr6,r0 ; r0, r6, r7 ? source page note : the above examples also apply to the instructions ldci and ldcpi. example 19 . a) ldw 40h,20h ; 20h, 21h ? source page ; 40h, 41h ? destination page b) ldw 60h,@20h ; 20h, 40h ? source page 20h contains 40h ; 60h, 61h ? destination page c) ldw 40h,#02h ; 40h, 41h ? destination page
s3c880a/f880a address spaces 2 - 13 f programming tip ? examples of inter-page data transfer operations (concluded) example 20 . a) mult 40h,20h ; 20h ? source page ; 40h, 41h ? destination page b) mult 60h,@20h ; 20h, 40h ? source page 20h contains 40h ; 60h, 61h ? destination page c) mult 40h,#02h ; 40h, 41h ? destination page example 21 . a) pop 00h ; 00h ? destination page b) pop @20h ; 20h ? source page 20h contains 40h ; 40h ? des tination page example 22 . a) popud 00h,@20h ; 20h, 40h ? source page 20h contains 40h ; 00h ? destination page note : the above example also applies to the instruction popui. example 23 . a) push 00h ; 00h ? destination page b) push @20h ; 20h, 40h ? source page 20h contains 40h example 24 . a) pushud @60h,20h ; 60h, 20h ? source page 60h contains 44h ; 44h ? destination page note : the above example also applies to the instruction pushui. example 25 . a) swap 00h ; 00h ? destination page b) swap @20h ; 20h ? source page 20h contains 40h ; 40h ? destination page
address spaces s3c880a/f880a 2 - 14 register set 1 the term set 1 refers to the upper 64 bytes of the register file, locations c0h?ffh. this area can be accessed at any time, regardless of which page is currently selected. the upper 32-byte area of this 64-byte space is divided into two 32-byte register banks, called bank 0 and bank 1 . you use the select register bank instructions, sb0 or sb1, to address one bank or the other. a reset operation automatically selects bank 0 addressing. the lower 32-byte area of set 1 is not banked. this area contains 16 bytes for mapped system registers (d0h?dfh) and a 16-byte common area (c0h?cfh) for working register addressing. registers in set 1 are directly accessible at all times using register addressing mode. the 16-byte working register area ,however, can only be accessed using working register addressing. working register addressing is a function of register addressing mode (see chapter 3, "addressing modes," for more information). register set 2 the same 64-byte physical space that is used for the set 1 register locations c0h?ffh is logically duplicated to add another 64 bytes. this expanded area of the register file is called set 2 . the logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: w hile you can access set 1 using register addressing mode only, you should use register indirect addressing mode or indexed addressing mode to access set 2. for the s3c880a/f880a , the set 2 address range (c0h?ffh) is accessible on page 0 and page 1. please note, however, that on page 1, the set 2 locations f c h?ffh are not mapped. part of the osd video ram is in page 1, set 2 (c0h?f b h), and the other part (00h?bfh) is in the page 1 prime register area. to avoid programming errors, we recommend using either register indirect or indexed mode to address the entire 2 52 -byte video ram area. prime register space the lower 192 bytes (00h?bfh) of the s3c880a/f880a 's two 256 -byte register pages and the 64 bytes (00h?3fh) of register page 2 are called prime register area. prime registers can be accessed using any of the seven addressing modes. the prime register area on page 0 is immediately addressable after a reset. in order to address registers on page 1 (in the osd video ram), you must first set the register page pointer (pp) to the appropriate source and destination values.
s3c880a/f880a address spaces 2 - 15 c0h 00h page 0 ffh set 2 prime space c0h 00h page 1 ffh set 2 prime space fbh ffh fch e0h d0h c0h set 1 bank 0 bank 1 peripheral and i/o general-purpose cpu and system control osd video ram area not mapped 3fh 00h page 2 ffh set 2 prime space figure 2 -6 . set 1, set 2, and prime area register map
address spaces s3c880a/f880a 2 - 16 working registers instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. when 4-bit working register addressing is used, the 256-byte register file is viewed as thirty two 8-byte register groups or "slices." each slice consists of eight 8-bit registers. when the two 8-bit register pointers, rp1 and rp0, are used, two working register slices can be selected at any time to form a 16-byte working register block. using the register pointers, you can move this 16-byte register block anywhere in the addressable register file (except for the set 2 area). the terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: ? one working register slice is 8 bytes (eight 8-bit working registers; r0?r7 or r8?r15) ? one working register block is 16 bytes (sixteen 8-bit working registers; r0?r15) all the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. this makes it possible for each register pointer to point to one of the 24 slices in the register file. the base addresses for the two selected 8-byte register slices are contained in the register pointers , rp0 and rp1. after a reset, rp0 and rp1 always point to the 16-byte common area in set 1 (c0h?cfh). each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block in total. 1 1 1 1 1 x x x rp1 (registers r8-r15) rp0 (registers r0-r7) slice 32 ~ ~ cfh c0h ffh f8h f7h f0h fh 8h 7h 0h slice 1 10h set 1 only 0 0 0 0 0 x x x figure 2 -7 . 8-byte working register areas (slices)
s3c880a/f880a address spaces 2 - 17 using the register pointers the r egister pointers , rp0 and rp1 , are mapped to the addresses d6h and d7h in set 1. they are used to select two movable 8-byte working register slices in the register file. after a reset, they point to the working register common area: rp0 points to the addresses c0h?c7h, and rp1 points to the addresses c8h?cfh. if you want to change a register pointer value, you should load a new value to rp0 and/or rp1 using an srp or ld instruction (see figures 2 - 7 and 2 - 8). with working register addressing, you can only access those locations that are pointed to by the register pointers. please note that you cannot use the register pointers to select the working register area in set 2, c0h?ffh, because these locations are accessible only using the indirect register or indexed addressing mode. the selected 16-byte working register block usually consists of two contiguous 8-byte slices. as a general programming guideline, we recommend that rp0 point to the "lower" slice and rp1 point to the "upper" slice (see figure 2 - 7). in some cases, it may be necessary to define working register areas in different (non-contiguous) areas of the register file. in figure 2 - 8, rp0 points to the "upper" slice and rp1 to the "lower" slice. because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area. f programming tip ? setting the register pointers srp #70h ; rp0 ? 70h, rp1 ? 78h srp1 #48h ; rp0 ? no change, rp1 ? 48h srp0 #0a0h ; rp0 ? a0h, rp1 ? no change clr rp0 ; rp0 ? 00h, rp1 ? no change ld rp1,#0f8h ; rp0 ? no change, rp1 ? 0f8h fh (r15) 0h (r0) 8-byte slice 16-byte contiguous working register block register file contains 32 8-byte slices 8-byte slice rp0 rp1 8h 7h 0 0 0 0 1 x x x 0 0 0 0 0 x x x figure 2 -8 . contiguous 16-byte working register block
address spaces s3c880a/f880a 2 - 18 8-byte slice 16-byte contiguous working register block register file contains 32 8-byte slices 8-byte slice 0h (r0) 7h (r15) f0h (r0) f7h (r7) rp1 rp0 1 1 1 1 0 x x x 0 0 0 0 0 x x x figure 2 -9 . non-contiguous 16-byte working register block f programming tip ? using the rps to calculate the sum of a series of registers calculate the sum of the registers , 80h?85h , using the register pointer. the register addresses 80h through 85h contain the values 10h, 11h, 12h, 13h, 14h, and 15 h, respectively: srp0 #80h ; rp0 ? 80h add r0,r1 ; r0 ? r0 + r1 adc r0,r2 ; r0 ? r0 + r2 + c adc r0,r3 ; r0 ? r0 + r3 + c adc r0,r4 ; r0 ? r0 + r4 + c adc r0,r5 ; r0 ? r0 + r5 + c the sum of these six registers, 6fh, is located in the register r0 (80h). the instruction strin g used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. if you do not use the register pointer to calculate the sum of these registers, you would have to execute the following instruction sequence: add 80h,81h ; 80h ? (80h) + (81h) adc 80h,82h ; 80h ? (80h) + (82h) + c adc 80h,83h ; 80h ? (80h) + (83h) + c adc 80h,84h ; 80h ? (80h) + (84h) + c adc 80h,85h ; 80h ? (80h) + (85h) + c here, the sum of the six registers is also located in the register 80h. t his instruction string , however, takes 15 bytes of instruction code rather than 12 bytes, and the execution time is 50 cycles rather than 36 cycles.
s3c880a/f880a address spaces 2 - 19 register addressing the sam8 register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. register (r) addressing mode, in which the operand value is the content of a specific register or register pair, can be used to access any location in the register file except for set 2. for working register addressing, the register pointers , rp0 and rp1 , are used to select a specific register within a selected 16-byte working register area. to increase the speed of context switches in an application program, the register pointers can be used to dynamically select different 8 -byte "slices" of the register file as the active working register space. registers are addressed either as a single 8-bit register or a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and that of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb rn lsb rn+1 n = even address figure 2 - 9. 16-bit register pairs
address spaces s3c880a/f880a 2 - 20 ffh d0h ffh c0h set 2 cfh d7h rp1 d6h rp0 register pointers c0h bfh 00h special-purpose registers general-purpose registers all addressing modes page 0, 1 indirect register, indexed addressing modes page 0, 1 register addressing only can be pointed by register pointer each register pointer (rp) can independently point to one of the twenty 8-byte "slices" of the register file (other than set 2). after a reset, rp0 points to locations c0h-c7h and rp1 to locations c8h-cfh (the common working register area). bank 1 prime registers control registers system registers set 1 bank 0 figure 2 - 1 1 . register file addressing
s3c880a/f880a address spaces 2 - 21 common working register area (c0h?cfh) after a reset, the register pointers , rp0 and rp1 , automatically point to two 8-byte register slices in set 1, locations c0h?cfh, as the active 16-byte working register block: rp0 ? c0h?c7h rp1 ? c8h?cfh this 16 - byte address range is a common area . that is, locations in this area can be accessed using working register addressing only. 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 rp0 = rp1 = register pointers rp0 and rp1 point to the common working register area (coh-cfh) after a reset. c0h 00h page 0 ffh set 2 prime area bfh ~ ~ set 1 ffh fch e0h cfh c0h dfh set 2 c0h 00h page 1 ffh prime area bfh ~ not used fbh ~ 00h page 2 ffh prime area 3fh ~ not used ~ figure 2 - 1 2 . common working register area
address spaces s3c880a/f880a 2 - 22 f programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. example s : 1. ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: srp #0c0h ld r2,40h ; r2 (c2h) ? the value in location 40h 2 . add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: srp #0c0h add r3,#45h ; r3 (c3h) ? r3 + 45h 4-bit working register addressing each register pointer defines a movable 8-byte slice of working register space. the address information stored in a register pointer serves as an addressing "window" that enables instructions to access working registers very efficiently using short 4-bit addresses. when an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: ? the high-order bit of the 4-bit addre ss selects one of the register pointers ("0" selects rp0; "1" selects rp1); ? the five high-order bits in the register pointer select an 8-byte slice of the register space; ? the three low-order bits of the 4-bit address select one of the eight registers in the slice. as shown in figure 2 - 12, the net effect of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form a complete address. as long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. figure 2 - 13 shows a typical example of 4-bit working register addressing: t he high-order bit of the instruction 'inc r6' is "0", which selects rp0. the five high-order bits stored in rp0 (01110b) are concatenated with the three low-order bits of the instruction's 4-bit address (110b) to produce the register address 76h (01110110b).
s3c880a/f880a address spaces 2 - 23 together they create an 8-bit register address register pointer provides five high-order bits address opcode selects rp0 or rp1 rp1 rp0 4-bit address procides three low-order bits figure 2 - 1 3 . 4-bit working register addressing register address (76h) rp0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 r6 0 1 1 0 1 1 1 0 selects rp0 instruction: 'inc r6' opcode rp1 0 1 1 1 1 0 0 0 figure 2 -14 . 4-bit working register addressing example
address spaces s3c880a/f880a 2 - 24 8-bit working register addressing you can also use 8-bit working register addressing to access registers in a selected working register area. in order to initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100b. this 4-bit value (1100b) indicates that the remaining four bits have the same effect as 4-bit working register addressing. as shown in figure 2 - 14, the lower nibble of the 8-bit address is concatenated in much the same way as for 4 -bit addressing: b it 3 selects either rp0 or rp1, which then supplies the five high-order bits of the final address, and the three low-order bits of the complete address are provided by the original instruction. figure 2 - 15 shows an example of 8-bit working register addressing: t he four high-order bits of the instruction address (1100b) specify 8-bit working register addressing. the fourth bit ("1") selects rp1 and the five high-order bits in rp1 (10100b) become the five high-order bits of the register address. the three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. together, the five address bits from rp1 and the three address bits from the instruction comprise the complete register address, r163 (10100011b). 8-bit physical address register pointer provides five high-order bits address selects rp0 or rp1 rp1 rp0 three low- order bits 8-bit logical address these address bits indicate 8-bit working register addressing 1 1 0 0 figure 2 - 1 5 . 8-bit working register addressing
s3c880a/f880a address spaces 2 - 25 8-bit address form instruction 'ld r11, r2' rp0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 selects rp1 r11 register address (0abh) rp1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 specifies working register addressing figure 2 -16 . 8-bit working register addressing example
address spaces s3c880a/f880a 2 - 26 system and user stacks the s3c 8-series microcontrollers use the system stack for subroutine calls and returns, interrupt processing, and data storage . the push and pop instructions support system stack operations. stack operations in the internal register file and in external data memory are supported by hardware. (the s3c880a/f880a do not support an external memory access.) bit 1 in the external memory timing register emt selects an internal or external stack area. the 16 -bit stack pointer register (sph, spl) is used to access an externally defined system stack. an 8-bit stack pointer (spl) is sufficient for internal stack addressing. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by an ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2 - 16. low address high address stack contects after a call instruction stack contects after an interrupt top of stack flags pch pcl pcl pch top of stack figure 2 - 1 7 . stack operations user-defined stacks you can freely define stacks in the internal register file as data storage locations. the instructions , pushui, pushud, popui, and popud , support user-defined stack operations. stack pointers (spl, sph) the r egister locations d8h and d9h contain the 16-bit stack pointer (sp) value. the most significant byte of a 16-bit stack address is stored in the sph register (d8h) and the least significant byte is stored in the spl register (d9h). because an external memory interface is not implemented for the s3c880a/f880a microcontrollers, a single 8-bit stack pointer (spl) is sufficient to address stack locations in the internal register file. after a reset, the stack pointer value is undetermined. the spl register must then be initialized to an 8 -bit value in the range 00h? ffh, page 0. you can use the sph register as a general-purpose data register. please note that when you do so, data stored in sph may be overwritten if an overflow or underflow of the spl register occurs during normal stack operations. to prevent this, you can initialize the spl value to ffh instead of 00h.
s3c880a/f880a address spaces 2 - 27 f programming tip ? standard stack operations using push and pop the following sample code shows how to perform stack operations in the internal register file using push and pop instructions: ld spl,#0ffh ; spl ? ffh (normally, the spl is set to 0ffh by the ? ; initialization routine) ? ? push pp ; stack address 0feh ? pp push rp0 ; stack address 0fdh ? rp0 push rp1 ; stack address 0fch ? rp1 push r3 ; stack address 0fbh ? r3 ? ? ? pop r3 ; r3 ? stack address 0fbh pop rp1 ; rp1 ? stack address 0fch pop rp0 ; rp0 ? stack address 0fdh pop pp ; pp ? stack address 0feh
address spaces s3c880a/f880a 2 - 28 notes
s3c880a/f880a addressing modes 3 - 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is used to determine the location of the data operand. the operands specified in sam87 instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam87 instruction set supports seven explicit addressing modes. not all of these addressing modes are available for each instruction. the addressing modes and their symbols are as follows: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? indire ct address (ia) ? relative address (ra) ? immediate (im)
addressing modes s3c880a/f880a 3 - 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register or register pair (see figure 3 - 1). working register addressing differs from register addressing as it uses a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space (see figure 3 - 2). dst value used in instruction execution opcode operand 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3 - 1. register addressing dst opcode 4-bit working register point to the working register (1 of 8) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 and r2 are registers in the curruntly selected working register area. program memory register file src 3 lsbs rp0 or rp1 selected rp points to start of working register block operand msb point to rp0 ot rp1 figure 3 - 2. working register addressing
s3c880a/f880a addressing modes 3 - 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, program memory (rom), or an external memory space (see figures 3 - 3 through 3 - 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. you cannot, however, access the locations c0h?ffh in set 1 using indirect register addressing mode. dst address of operand used by instruction opcode address 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3 - 3. indirect register addressing to register file
addressing modes s3c880a/f880a 3 - 4 indirect register addressing mode (c ontinued ) dst opcode pair points to register pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3 - 4. indirect register addressing to program memory
s3c880a/f880a addressing modes 3 - 5 indirect register addressing mode (c ontinued ) dst opcode address 4-bit working register address point to the working register (1 of 8) sample instruction: or r3, @r6 program memory register file src 3 lsbs value used in instruction operand selected rp points to start of working register block rp0 or rp1 msb points to rp0 or rp1 figure 3 - 5. indirect working register addressing to register file
addressing modes s3c880a/f880a 3 - 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 2-bit point to working register pair (1 of 4) lsb selects register pair 16-bit address points to program memory or data memory rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block figure 3 - 6. indirect working register addressing to program or data memory
s3c880a/f880a addressing modes 3 - 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during the instruction execution in order to calculate the effective operand address (see figure 3 - 7). you can use indexed addressing mode to access locations in the internal register file or in external memory. you cannot, however, access the locations c0h?ffh in set 1 using indexed addressing mode. in short offset indexed addressing mode, the 8 -bit displacement is treated as a signed integer in the range ? 128 to + 127. this applies to external memory accesses only (see figure 3 - 8) . for register file addressing, an 8 -bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3 - 9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory and for external data memory, when implemented. dst/src opcode two-operand instruction example point to one of the working register (1 of 8) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file x 3 lsbs value used in instruction operand index base address rp0 or rp1 selected rp points to start of working register block + figure 3 - 7. indexed addressing to register file
addressing modes s3c880a/f880a 3 - 8 indexed addressing mode (c ontinued ) register file operand program memory or data memory point to working register pair (1 of 4) lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block dst/src opcode program memory x offset 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + 04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits + figure 3 - 8. indexed addressing to program or data memory with short offset
s3c880a/f880a addressing modes 3 - 9 indexed addressing mode (c oncluded ) register file operand program memory or data memory point to working register pair lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + 1000h) are loaded into register r4. lde r4,#1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register fair value used in instruction 8-bits 16-bits 16-bits dst/src opcode program memory src offset 4-bit working register address offset + figure 3 - 9. indexed addressing to program or data memory
addressing modes s3c880a/f880a 3 - 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or the destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3 - 10. direct addressing for load instructions
s3c880a/f880a addressing modes 3 - 11 direct address mode (c ontinued ) opcode program memory lower address byte memory address used upper address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3 - 11. direct addressing for call and jump instructions
addressing modes s3c880a/f880a 3 - 12 indirect address mode (ia) in indirect address (ia) mode, the instruction specifies an address located in the lowe r 256 bytes of the program memory. the selected pair of memory locations contains the actual address of the next instruction to be executed. only the call instruction can use indirect address mode. as indirect address mode assumes that the operand is located in the lowe r 256 bytes of the program memory, only an 8-bit address is provided in the instruction; the upper bytes of the destination address are assumed to be all zeros. current instruction program memory locations 0-255 program memory opcode dst lower address byte upper address byte next instruction lsb must be zero sample instruction: call #40h ; the 16-bit value in program memory addresses 40h and 41h is the subroutine start address. figure 3 - 12. indirect addressing
s3c880a/f880a addressing modes 3 - 13 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. several program control instructions use relative address mode to perform conditional jumps. the instructions that support ra addressing are btjrf, btjrt, djnz, cpije, cpijne, and jr. opcode program memory displacement program memory address used sample instructions: jr ult,$+offset ; where offset is a value in the range +127 to -128 next opcode + signed displacement value current instruction current pc value figure 3 - 13. relative addressing
addressing modes s3c880a/f880a 3 - 14 immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. the operand may be one byte or one word in length, depending on the instruction used. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3 - 14. immediate addressing
s3c880a/f880a control registers 4 - 1 4 control registers overview in this chapter , detailed descriptions of the s3c880a/f880a control registers are presented in an easy-to-read format. these descriptions will help familiarize you with the mapped locations in the register file. you can also use them as a quick-reference source when writing application programs. system and peripheral registers are summarized in tables 4 - 1, 4 - 2, and 4 - 3. figure 4 - 1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more information about control registers is presented in the context of the various peripheral hardware descriptions in part ii of this manual.
control registers s3c880a/f880a 4 - 2 table 4 - 1. set 1 registers register name mnemonic decimal hex r/w timer 0 counter t0cnt 208 d0h r timer 0 data register t0data 209 d1h r/w timer 0 control register t0con 210 d2h r/w basic timer control register btcon 211 d3h r/w clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w register pointer 0 rp0 214 d6h r/w register pointer 1 rp1 215 d7h r/w stack pointer (high byte) sph 216 d8h r/w stack pointer (low byte) spl 217 d9h r/w instruction pointer (high byte) iph 218 dah r/w instruction pointer (low byte) ipl 219 dbh r/w interrupt request register irq 220 dch r interrupt mask register imr 221 ddh r/w system mode register sym 222 deh r/w register page pointer pp 223 dfh r/w table 4 - 2. set 1, bank 0 registers register name mnemonic decimal hex r/w port 0 data register p0 224 e0h r/w port 1 data register p1 225 e1h r/w port 2 data register p2 226 e2h r/w port 3 data register p3 227 e3h r/w port 0 control register (high byte) p0conh 228 e4h r/w port 0 control register (low byte) p0conl 229 e5h r/w port 1 control register (high byte) p1conh 230 e6h r/w port 1 control register (low byte) p1conl 231 e7h r/w port 2 control register (high byte) p2conh 232 e8h r/w port 2 control register (low byte) p2conl 233 e9h r/w location eah in set 1, bank 0, are not mapped. port 3 control register (low byte) p3conl 235 ebh r/w locations ech - eeh in set 1, bank 0, are not mapped. pll control register (note) pllcon 236 efh r/w note: pll control register, pllcon, is a system register for factory test. so user should not access this register.
s3c880a/f880a control registers 4 - 3 table 4 - 2. set 1, bank 0 registers (continued) register name mnemonic decimal hex r/w timer a data register tadata 240 f0h r/w location f1h in set 1, bank 0, are not mapped. stop control register stcon 238 f3h r/w timer a control register tacon 242 f2h r/w pwm0 data register (main byte) pwm0 244 f4h r/w pwm0 data register (extension byte) pwm0ex 245 f5h r/w pwm1 data register (main byte) pwm1 246 f6h r/w pwm1 data register (extension byte) pwm1ex 247 f7h r/w pwm control register pwmcon 248 f8h r/w capture a data register capa 249 f9h r a/d converter control register adcon 250 fah r/w (2) a/d conversion data register addata 251 fbh r test control register tstc 252 fch r/w (1) basic timer counter btcnt 253 fdh r external memory timing register emt 254 feh r/w interrupt priority register ipr 255 ffh r/w note : test control regi ster, tstc, is a system register for factory test. so user should not access this register.
control registers s3c880a/f880a 4 - 4 table 4 - 3. set 1, bank 1 registers register name mnemonic decimal hex r/w osd fringe/border control register 1 osdfrg1 224 e0h r/w osd fringe/border control register 2 osdfrg2 225 e1h r/w osd smooth control register 1 osdsmh1 226 e2h r/w osd smooth control register 2 osdsmh2 227 e3h r/w osd space color control register osdcol 236 e4h r/w osd field control register osdfld 237 e5h r/w osd palette color mode r 1 osdpltr1 230 e6h r/w osd palette color mode r 2 osdpltr2 231 e7h r/w osd palette color mode g 1 osdpltg1 232 e8h r/w osd palette color mode g 2 osdpltg2 233 e9h r/w osd palette color mode b 1 osdpltb1 234 eah r/w osd palette color mode b 2 osdpltb2 235 ebh r/w locations ech?efh in set 1, bank 1, are not mapped. osd character size control register chacon 240 f0h r/w osd fade control register fadecon 241 f1h r/w osd row position control register rowcon 242 f2h r/w osd column position control register clmcon 243 f3h r/w osd background color control register colcon 244 f4h r/w on-screen display control register dspcon 245 f5h r/w halftone signal control register htcon 246 f6h r/w v-sync blank control register vsbcon 251 f7h r/w pwm2 data register pwm2 247 f8h r/w pwm3 data register pwm3 248 f9h r/w pwm4 data register pwm4 249 fah r/w pwm5 data register pwm5 250 fbh r/w osd color buffer colbuf 252 fch r/w locations fdh?ffh in set 1, bank 1, are not mapped.
s3c880a/f880a control registers 4 - 5 flags ? system flags register d5h set 1 bit identifie r reset value read/write addressing mode .7 .6 carry flag (c) 0 1 operation does not generate a carry or borrow condition operation generates a carry-out or a borrow condition in high-order bit 7 register mnemonic full register name register address (hexadecimal) bit number: msb = bit 7 lsb = bit 0 r w r/w '?' = = = = read-only write-only read/write not used bit number(s) that is/are appended to the register name for bit addressing description of the effect of specific bit settings name of an individual bit or bit function addressing mode or modes you can use to modify register values register addressing mode only .7 .6 .5 .4 .3 .2 .1 .0 x x x x x x 0 0 r/w r/w r/w r/w r/w r/w r/w r/w not used undetermined value logic zero logic one '?' 'x' '0' '1' = = = = reset value notation: register location in the internal register file zero flag (z) 0 1 operation result is a non-zero value operation result is zero sign flag (s) 0 1 operation generates a positive number (msb = "0") operation generates a negative number (msb = "1") .5 figure 4 - 1. register description format
control registers s3c880a/f880a 4 - 6 adcon ? a/d converter control register fah set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value ? ? 0 0 x 0 0 0 read/write ? ? r/w r/w r r /w r /w r /w addressing mode register addressing mode only .7?.6 not used for the s3c880a/f880a .5?.4 a/d converter input pin selection bits 0 0 adc0 (p3.0) 0 1 adc1 (p3.1) 1 0 adc2 (p0.6) 1 1 adc3 (p0.7) .3 end-of-conversion status bit (read only) 0 a/d conversion is in progress 1 a/d conversion complete . 2 and .1 clock source selection bits 0 0 fosc/16 (fosc < 8 mhz) 0 1 fosc/8 (fosc < 8 mhz) 1 0 fosc/14(fosc < 8 mhz) 1 1 fosc/2 (fosc < 8 mhz) .0 conversion start bit 0 no meaning 0 a/d conversion start
s3c880a/f880a control registers 4 - 7 btcon ? basic timer control register d3h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .4 watchdog timer function disable code (for reset) 1 0 1 0 disable watchdog timer function others enable watchdog timer function .3 and .2 basic timer input clock selection bits 0 0 f osc /4096 0 1 f osc /1024 1 0 f osc /128 1 1 invalid selection .1 basic timer counter clear bit ( note ) 0 no effect 1 clear the basic timer counter value .0 clock divider clear bit for basic timer and timer 0 ( note ) 0 no effect 1 clear both dividers note : when you write a "1" to bit 0 or bit 1, the corresponding divider or counter value is cleared to '00h'. the corresponding btcon bit is then automatically reset by hardware to "0".
control registers s3c880a/f880a 4 - 8 chacon ? osd character size control register f0h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 vertical character size selection bits 0 0 select 'x1' vertical character size 0 1 select 'x2' vertical character size 1 0 select 'x3' vertical character size 1 1 select 'x4' vertical character size .5 and .4 horizontal character size selection bits 0 0 select 'x1' horizontal character size 0 1 select 'x2' horizontal character size 1 0 select 'x3' horizontal character size 1 1 select 'x4' horizontal character size .3 ? .0 fade row address selection for rows 0? 11 in on-screen display 0 0 0 0 row 0 selected 0 0 0 1 row 1 selected 0 0 1 0 row 2 selected 0 0 1 1 row 3 selected 0 1 0 0 row 4 selected 0 1 0 1 row 5 selected 0 1 1 0 row 6 selected 0 1 1 1 row 7 selected 1 0 0 0 row 8 selected 1 0 0 1 row 9 selected 1 0 1 0 row 10 selected 1 0 1 1 row 11 selected others invalid selection
s3c880a/f880a control registers 4 - 9 clkcon ? system clock control register d4h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 oscillator irq wake-up function enable bit 0 enable irq for main system oscillator wake-up in power-down mode 1 disable irq for main system oscillator wake-up in power-down mode .6 and .5 main oscillator stop control bits 0 0 no effect 0 1 no effect 1 0 stop main oscillator 1 1 no effect .4 and .3 cpu clock (system clock) selection bits (1) 0 0 divide by 16 (f osc /16) 0 1 divide by 8 (f osc /8) 1 0 divide by 2 (f osc /2) 1 1 non-divided clock (f osc ) .2 ?. 0 subsystem clock selection bits (2) 1 0 1 invalid selection for s3c880a/f880a others select main system clock (mclk) notes : 1. after a reset, the slowest clock (divide by 16) is selected as the system clock. to select faster clock spe eds, load the appropriate values to clkcon.3 and clkcon.4. 2. these selection bits are required only for systems that have a main clock and a subsystem clock. the s3c880a/f880a microcontrollers have only a main oscillator (and an l-c oscillator for the osd module). for this reason, the setting '101b' is invalid.
control registers s3c880a/f880a 4 - 10 clmcon ? osd column control register f3h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .3 left margin display position control bits (1 6 + 4 x lmg value of 0?31 dots) 0 0 0 0 0 left margin = 1 6 dot clocks 0 0 0 0 1 left margin = 1 6 + 4 1 dot clock ? ? ? ? ? ? 1 1 1 1 1 left margin = 1 6 + 4 31 dot clocks .2 ? .0 inter-column spacing control selection (0?7 dots) 0 0 0 no inter-column spacing 0 0 1 inter-column spacing = 1 dot ? ? ? ? ? ? 1 1 1 inter-column spacing = 7 dots note : to set left margin and inter-column spacing, separate decimal values must be calculated, converted to their binary equivalents, and then written to the clmcon register.
s3c880a/f880a control registers 4 - 11 colbuf ? osd character color buffer f c h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value ? ? ? x x x x x read/write ? ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ?.6 not used for the s3c880a/f880a. .5 video ram bit-9 enable bit 0 disable vram bit-9 1 enable vam bit-9 .4 video ram bit-8 enable bit 0 disable vram bit-8 1 enable vram bit-8 . 3 h/t and bgrnd enable bit 0 disable h/t and brgnd 1 enable h/t and brgnd .2 ? .0 character color selection bits .2 .1 .0 osdcol.0 = 0 osdcol.0 = 1 0 0 0 black color mode 0 0 0 1 blue color mode 1 0 1 0 green color mode 2 0 1 1 cyan color mode 3 1 0 0 red color mode 4 1 0 1 magenta color mode 5 1 1 0 yellow color mode 6 1 1 1 white color mode 7
control registers s3c880a/f880a 4 - 12 colcon ? osd background color control register f4h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 frame background color enable bit 0 disable frame background color (no background color is displayed) 1 enable frame background color .6 ? .4 frame background color selection bits (when .7 = "1") .6 .5 .4 osdcol.0 = 0 osdcol.0 = 1 0 0 0 black color mode 0 0 0 1 blue color mode 1 0 1 0 green color mode 2 0 1 1 cyan color mode 3 1 0 0 red color mode 4 1 0 1 magenta color mode 5 1 1 0 yellow color mode 6 1 1 1 white color mode 7 .3 character background color enable bit 0 disable character background color (no background color is displayed) 1 enable character background color display .2 ? .0 character background color selection bits (when .3 = "1") .2 .1 .0 osdcol.0 = 0 osdcol.0 = 1 0 0 0 black color mode 0 0 0 1 blue color mode 1 0 1 0 green color mode 2 0 1 1 cyan color mode 3 1 0 0 red color mode 4 1 0 1 magenta color mode 5 1 1 0 yellow color mode 6 1 1 1 white color mode 7
s3c880a/f880a control registers 4 - 13 dspcon ? on-screen display control register f5h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r r r r r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 osd row counter (read-only) 0 0 0 0 row 0 0 0 0 1 row 1 0 0 1 0 row 2 0 0 1 1 row 3 0 1 0 0 row 4 0 1 0 1 row 5 0 1 1 0 row 6 0 1 1 1 row 7 1 0 0 0 row 8 1 0 0 1 row 9 1 0 1 0 row 10 1 0 1 1 row 11 others 1100-1111 are not used .3 clock edge selection for h/v-sync polarity 0 rising edge 1 falling edge .2?.1 halftone or background color selection bits 0 0 character background color 0 1 not used 1 0 halftone output 1 1 character halftone and background color .0 display enable bit 0 disable osd (turn off l-c osc) 1 enable osd (turn on l-c osc)
control registers s3c880a/f880a 4 - 14 emt ? external memory timing register feh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? addressing mode register addressing mode only .7 external n wait input function enable bit 0 disable n wait input function for external device (normal operating mode) 1 enable n wait input function for external device .6 slow memory timing enable bit 0 disable slow memory timing 1 enable slow memory timing .5 and .4 program memory automatic wait control bits 0 0 no wait (normal operation) 0 1 wait one cycle 1 0 wait two cycles 1 1 wait three cycles .3 and .2 data memory automatic wait control bits 0 0 no wait (normal operation) 0 1 wait one cycle 1 0 wait two cycles 1 1 wait three cycles .1 stack area selection bit 0 select internal register file area 1 select external data memory area .0 not used for the s3c880a/f880a. note: because an external interface is not implemented for the s3c880a/f880a , the emt values should always be "0".
s3c880a/f880a control registers 4 - 15 fadecon ? osd fade control register f1h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 not used for the s3c880a/f880a. .6 fade function enable bit 0 fade disable 1 fade enable .5 fade direction selection bit 0 fade before matrix 1 fade after matrix .4 ? .0 halftone or background color selection bits (1) 0 0 0 0 0 line 0 0 0 0 0 1 line 1 . . . . . . . . 1 0 0 0 0 line 16 1 0 0 0 1 line 17 1 0 0 1 0 inter-row space line 1 (1h) 1 0 0 1 1 inter-row space line 2 (1h) 1 0 1 0 0 inter-row space line 3 (1h) 1 0 1 0 1 inter-row space line 4 (1h) 1 0 1 1 0 inter-row space line 5 (1h) 1 0 1 1 1 inter-row space line 6 (1h) 1 1 0 0 0 inter-row space line 7 (1h) 1 1 0 0 1 not used . . . . . . . . 1 1 1 1 1 not used note: there are two choices of fade direction: before (fadecon.5="0") and after (fadecon.5="1"). when you select fade before, the character matrix is faded starting with current line +1 (not including current line). when you select fade after, the character matrix is faded starting with current line.
control registers s3c880a/f880a 4 - 16 flags ? system flags register d5h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value x x x x x x 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 carry flag (c) 0 operation does not generate a carry or borrow condition 1 operation generates a carry-out or borrow into high-order bit - 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is + 127 or 3 ? 128 1 operation result is > + 127 or < ? 128 .3 decimal adjust flag (d) 0 add operation has completed 1 subtraction operation has completed .2 half-carry flag (h) 0 no carry-out of bit 3 or no borrow into bit 3 by addition or subtraction 1 addition generated carry-out of bit 3 or subtraction generated borrow into bit 3 .1 fast interrupt status flag (fis) 0 cleared automatically during an interrupt return (iret) 1 automatically set to logic one during a fast interrupt service routine .0 bank address selection flag (ba) 0 bank 0 is selected (using the sb0 instruction) 1 bank 1 is selected (using the sb1 instruction)
s3c880a/f880a control registers 4 - 17 htcon ? halftone signal control register f6h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 halftone output polarity selection bit (ht only) 0 active high (normal halftone output is low level) 1 active low (normal halftone output is high level) .6 rgb output polarity selection bit 0 active high (normal rgb polarity is low level) 1 active low (normal rgb polarity is high level) .5 osd row interrupt enable bit 0 disable the osd row interrupt 1 enable the osd row interrupt .4 osd row interrupt pending bit 0 no interrupt is pending (when read); clear pending bit (when write) 1 interrupt is pending (when read); no effect (when write) .3 halftone function enable bit 0 disable the halftone control signal 1 enable the halftone control signal .2 halftone option selection bit 0 halftone output for character periods only (as selected by video ram bit -13 ) 1 halftone output for all frame periods (regardless of video ram bit -13 setting) .1 v-sync interrupt enable bit 0 disable the v-sync interrupt 1 enable the v-sync interrupt .0 v-sync interrupt pending bit 0 no osd row interrupt is pending (when read) 0 clear pending bit (when write) 1 osd row interrupt is pending (when read) 1 no effect (when write)
control registers s3c880a/f880a 4 - 18 imr ? interrupt mask register ddh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value x x ? x x x x x read/write r/w r/w ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 interrupt priority level 7 (irq7) enable bit; v-sync 0 disable irq7 interrupt 1 enable irq7 interrupt .6 interrupt priority level 6 (irq 6 ) enable bit; timer a 0 disable irq6 interrupt 1 enable irq6 interrupt .5 not used for s3c880a/f880a .4 interrupt priority level 4 (irq 4 ) enable bit; p1.2 and p1.3 external interrupt 0 disable irq4 interrupt 1 enable irq 4 interrupt .3 interrupt priority level 3 (irq3) enable bit; capa 0 disable irq3 interrupt 1 enable irq3 interrupt .2 interrupt prior ity level 2 (irq2) enable bit; osd row interrupt 0 disable irq2 interrupt 1 enable irq2 interrupt .1 interrupt priority level 1 (irq1) enable bit; p 1.0 and p 1.1 external interrupt 0 disable irq1 interrupt 1 enable irq1 interrupt .0 interrupt priority level 0 (irq0) enable bit; t0int (match) 0 disable irq0 interrupt 1 enable irq0 interrupt
s3c880a/f880a control registers 4 - 19 iph ? instruction pointer (high byte) dah set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .0 instruction pointer address (high byte) the high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (ip15?ip8). the lower byte of the ip address is located in the ipl register (dbh). ipl ? instruction pointer (low byte) dbh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .0 instruction pointer address (low byte) the low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (ip7?ip0). the upper byte of the ip address is located in the iph register (dah).
control registers s3c880a/f880a 4 - 20 ipr ? interrupt priority register ffh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value x x ? x x x x x read/write r/w r/w ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7, .4, and .1 priority control bits for interrupt groups a, b, and c (1) 0 0 0 group priority undefined 0 0 1 b > c > a 0 1 0 a > b > c 0 1 1 b > a > c 1 0 0 c > a > b 1 0 1 c > b > a 1 1 0 a > c > b 1 1 1 group priority undefined .6 interrupt group c priority control bit 0 irq6 > irq7 1 irq7 > irq6 .5 not used for the s3c880a/f880a (2) .3 interrupt sub group b priority control bit 0 irq 3 > irq 4 1 irq 4 > irq 3 .2 interrupt group b priority control bit 0 irq2 > (irq3, irq4) 1 ( irq 3, irq4) > irq2 .0 interrupt group a priority control bit 0 irq0 > irq1 1 irq1 > irq0 notes: 1. interrupt group a is irq0 and irq1; interrupt group b is irq2, irq3, and irq4; interrupt group c is irq6 and irq7. 2. interrupt level irq5 is not used in the s3c880a/f880a interrupt structure. for this reason, ipr.5 is not used.
s3c880a/f880a control registers 4 - 21 irq ? interrupt request register dch set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 ? 0 0 0 0 0 read/write r r ? r r r r r addressing mode register addressing mode only .7 interrupt level 7 (irq7) request pending bit; v-sync 0 no irq7 interrupt pending 1 irq7 interrupt is pending .6 interrupt level 6 (irq6) request pending bit; timer a 0 no irq6 interrupt pending 1 irq6 interrupt is pending .5 not used for the s3c880a/f880a .4 interrupt level 4 (irq 4 ) request pending bit; p1.2 and p1.3 external interrupt 0 no irq 4 interrupt pending 1 irq 4 interrupt is pending .3 interrupt level 3 (irq3) request pending bit; capa 0 no irq3 interrupt pending 1 irq3 interrupt is pending .2 interrupt level 2 (irq2) request pending bit; osd row interrupt 0 no irq2 interrupt pending 1 irq2 interrupt is pending .1 interrupt level 1 (irq1) request pending bit; p 1.0 and p 1.1 external interrupt 0 no irq1 interrupt pending 1 irq1 interrupt is pending .0 interrupt level 0 (irq0) re quest pending bit; t0int (match ) 0 no irq0 interrupt pending 1 irq0 interrupt is pending note : interrupt level request pending bits can be polled by software t o detect an interrupt request pending condition on any of the seven valid interrupt levels (irq0?irq 4 , irq6, and irq7). interrupt pending bits are read-only addressable.
control registers s3c880a/f880a 4 - 22 osdcol ? osd space color control register e4 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value ? ? ? 0 0 0 0 0 read/write ? ? ? r/w r /w r /w r /w r /w addressing mode register addressing mode only .7 ?,5 not used for the s3c880a/f880a. .4 inter character smoothing control bit (note) 0 disable inter character smoothing 1 enable inter character smoothing .3 fringe dot size selection bit 0 1 dot 1 1/2 dot .2 inter-row space half tone 0 depend on character background half tone 1 depend on frame background half tone .1 inter-row space color 0 depend on character background color 1 depend on frame background color .0 rgb output selection bit 0 digital rgb output (disable palette color mode) 1 analog rgb output (enable palette color mode) note : in 1-dot fringe mode (osdcol.3 = ?0?) , inter-character smooth function is disabled.
s3c880a/f880a control registers 4 - 23 osdfld ? osd field control register e5 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value ? ? x 0 0 1 1 0 read/write ? ? r r/w r /w r /w r /w r /w addressing mode register addressing mode only .7 ?,6 not used for the s3c880a/f880a. .5 field data (read only) 0 even field 1 odd field .4 h-sync detect position select bit 0 detect h-sync before v-sync 1 detect h-sync after v-sync .3?.0 even field range 0 0 0 0 not used 0 0 0 1 f cpu /16 1 0 0 1 0 f cpu /16 2 0 0 1 1 f cpu /16 3 0 1 0 0 f cpu /16 4 0 1 0 1 f cpu /16 5 0 1 1 0 f cpu /16 6 (reset value) 0 1 1 1 f cpu /16 7 1 0 0 0 f cpu /16 8 1 0 0 1 f cpu /16 9 1 0 1 0 f cpu /16 10 1 0 1 1 f cpu /16 11 1 1 0 0 f cpu /16 12 1 1 0 1 f cpu /16 13 1 1 1 0 f cpu /16 14 1 1 1 1 f cpu /16 15
control registers s3c880a/f880a 4 - 24 osdfrg1 ? osd fringe/border control register 1 e0 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r /w r /w r /w r /w addressing mode register addressing mode only .7?.0 fringe/border function enable bit 0 disable fringe/border function at row n (n = 0?7) 1 enable fringe/border function at row n (n = 0?7) note: row n is respectively correspond with bit n (n = 0?7).
s3c880a/f880a control registers 4 - 25 osdfrg2 ? osd fringe/border control register 2 e1 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r /w r /w r /w r /w addressing mode register addressing mode only .7 fringe or border selection bit 0 border function select 1 fringe function select .6?.4 fringe/border color selection bits (.6: red, .5: green, .4: blue) .6 .5 .4 osdcol.0 = 0 osdcol.0 = 1 0 0 0 black color mode 0 0 0 1 blue color mode 1 0 1 0 green color mode 2 0 1 1 cyan color mode 3 1 0 0 red color mode 4 1 0 1 magenta color mode 5 1 1 0 yellow color mode 6 1 1 1 white color mode 7 .3?.0 fringe/border function enable bits 0 disable fringe/border function at row n (n = 8?11) 1 enable fringe/border function at row n (n = 8?11) note: row 8, row 9, row 10, row 11 are correspond with bit 0, bit 1, bit 2, bit3, respectively.
control registers s3c880a/f880a 4 - 26 osdpltb1 ? osd palette color mode register b1 ea h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 1 1 0 0 1 1 0 0 read/write r/w r/w r/w r/w r /w r /w r /w r /w addressing mode register addressing mode only .7?.6 osd mode 3 blue level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .5?.4 osd mode 2 blue level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .3?.2 osd mode 1 blue level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .1?.0 osd mode 1 blue level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 %
s3c880a/f880a control registers 4 - 27 osdpltb2 ? osd palette color mode register b2 eb h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 1 1 0 0 1 1 0 0 read/write r/w r/w r/w r/w r /w r /w r /w r /w addressing mode register addressing mode only .7?.6 osd mode 7 blue level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .5?.4 osd mode 6 blue level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .3?.2 osd mode 5 blue level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .1?.0 osd mode 4 blue level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 %
control registers s3c880a/f880a 4 - 28 osdpltg1 ? osd palette color mode register g1 e8 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 1 1 1 1 0 0 0 0 read/write r/w r/w r/w r/w r /w r /w r /w r /w addressing mode register addressing mode only .7?.6 osd mode 3 green level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .5?.4 osd mode 2 green level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .3?.2 osd mode 1 green level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .1?.0 osd mode 1 green level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 %
s3c880a/f880a control registers 4 - 29 osdpltg2 ? osd palette color mode register g2 e9 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 1 1 1 1 0 0 0 0 read/write r/w r/w r/w r/w r /w r /w r /w r /w addressing mode register addressing mode only .7?.6 osd mode 7 green level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .5?.4 osd mode 6 green level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .3?.2 osd mode 5 green level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .1?.0 osd mode 4 green level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 %
control registers s3c880a/f880a 4 - 30 osdpltr1 ? osd palette color mode register r1 e6 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r /w r /w r /w r /w addressing mode register addressing mode only .7?.6 osd mode 3 red level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .5?.4 osd mode 2 red level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .3?.2 osd mode 1 red level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .1?.0 osd mode 1 red level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 %
s3c880a/f880a control registers 4 - 31 osdpltr2 ? osd palette color mode register r2 e7 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r /w r /w r /w r /w addressing mode register addressing mode only .7?.6 osd mode 7 red level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .5?.4 osd mode 6 red level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .3?.2 osd mode 5 red level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 % .1?.0 osd mode 4 red level 0 0 disable 0 1 33 % 1 0 66 % 1 1 100 %
control registers s3c880a/f880a 4 - 32 osdsmh1 ? osd smooth control register 1 e2 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r /w r /w r /w r /w addressing mode register addressing mode only .7 row 7 smooth function enable bit 0 disable smooth function at row 7 1 enable smooth function at row 7 .6 row 6 smooth function enable bit 0 disable smooth function at row 6 1 enable smooth function at row 6 .5 row 5 smooth function enable bit 0 disable smooth function at row 5 1 enable smooth function at row 5 .4 row 4 smooth function enable bit 0 disable smooth function at row 4 1 enable smooth function at row 4 .3 row 3 smooth function enable bit 0 disable smooth function at row 3 1 enable smooth function at row 3 .2 row 2 smooth function enable bit 0 disable smooth function at row 2 1 enable smooth function at row 2 .1 row 1 smooth function enable bit 0 disable smooth function at row 1 1 enable smooth function at row 1 .0 row 0 smooth function enable bit 0 disable smooth function at row 0 1 enable smooth function at row 0
s3c880a/f880a control registers 4 - 33 osdsmh2 ? osd smooth control register 2 e3 h set 1 , bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r /w r /w r /w r /w addressing mode register addressing mode only .7 ?,4 not used for the s3c880a/f880a .3 row 11 smooth function enable bit 0 disable smooth function at row 11 1 enable smooth function at row 11 .2 row 10 smooth function enable bit 0 disable smooth function at row 10 1 enable smooth function at row 10 .1 row 9 smooth function enable bit 0 disable smooth function at row 9 1 enable smooth function at row 9 .0 row 8 smooth function enable bit 0 disable smooth function at row 8 1 enable smooth function at row 8
control registers s3c880a/f880a 4 - 34 p0conh ? port 0 control register (high byte) e4h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 1 1 1 1 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 p ort 0.7 configuration bits 0 0 input mode 0 1 adc input mode 1 0 open-drain output mode 1 1 open-drain output mode .5 and .4 port 0.6 configuration bits 0 0 input mode 0 1 adc input mode 1 0 open-drain output mode 1 1 open-drain output mode .3 and .2 port 0.5 configuration bits 0 0 input mode 0 1 input mode 1 0 push-pull output mode 1 1 push-pull output mode .1 and .0 port 0 .4 configuration bits 0 0 input mode 0 1 input mode 1 0 push-pull output mode 1 1 push-pull output mode
s3c880a/f880a control registers 4 - 35 p0conl ? port 0 control register (low byte) e5h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 port 0.3 configuration bits 0 0 input mode 0 1 input mode 1 0 n-channel open-drain output mode (5 v load) 1 1 push-pull output mode .5 and .4 port 0.2 configuration bits 0 0 input mode 0 1 input mode 1 0 n-channel open-drain output mode (5 v load) 1 1 push-pull output mode .3 and .2 port 0.1 configuration bits 0 0 input mode 0 1 input mode 1 0 n-channel open-drain output mode (5 v load) 1 1 push-pull output mode .1 and .0 port 0.0 configuration bits 0 0 input mode 0 1 input mode 1 0 n-channel open-drain output mode (5 v load) 1 1 push-pull output mode
control registers s3c880a/f880a 4 - 36 p1conh ? port 1 control register (high byte) e6h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 port 1.7 /t0ck configuration bits 0 0 input mode 0 1 timer 0 clock input mode 1 0 push-pull output mode 1 1 push-pull output mode .5 and .4 port 1.6 configuration bits 0 0 input mode 0 1 input mode 1 0 push-pull output mode 1 1 push-pull output mode .3 and .2 port 1.5 configuration bits 0 0 input mode 0 1 input mode 1 0 n-channel open-drain mode (6-volt load capacity) 1 1 n-channel open-drain mode (6-volt load capacity) .1 and .0 port 1.4 c onfiguration bits 0 0 input mode 0 1 input mode 1 0 n-channel open-drain mode (6-volt load capacity) 1 1 n-channel open-drain mode (6-volt load capacity)
s3c880a/f880a control registers 4 - 37 p1conl ? port 1 control register (low byte) e7h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 port 1.3 /int3 configuration bits 0 0 input mode ; interrupt disabled 0 1 input mode; interrupt on rising edge 1 0 input mode ; interrupt on falling edge 1 1 n-channel open-drain output mode (6-volt load capacity) .5 and .4 port 1.2 /int2 configuration bits 0 0 input mode ; interrupt disabled 0 1 input mode; interrupt on rising edge 1 0 input mode ; interrupt on falling edge 1 1 n-channel open-drain output mode (6-volt load capacity) .3 and .2 port 1.1 /int1 configuration bits 0 0 input mode ; interrupt disabled 0 1 input mode; interrupt on rising edge 1 0 input mode ; interrupt on falling edge 1 1 n-channel open-drain output mode (6-volt load capacity) .1 and .0 port 1.0/int0 configuration bits 0 0 input mode ; interrupt disabled 0 1 input mode; interrupt on rising edge 1 0 input mode ; interrupt on falling edge 1 1 n-channel open-drain output mode (6-volt load capacity)
control registers s3c880a/f880a 4 - 38 p2conh ? port 2 control register (high byte) e8h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 port 2.7/ osdht configuration bits 0 0 input mode 0 1 n-channel open-drain output mode ( 5 -volt load capacity) 1 0 push-pull output mode 1 1 osd half-tone output mode (push-pull circuit type) .5 and .4 port 2.6 /t0 configuration bits 0 0 input mode 0 1 n-channel open-drain output mode ( 5 -volt load capacity) 1 0 push-pull output mode 1 1 timer 0 output mode (interval or pwm; n-channel open-drain type) .3 and .2 port 2.5/ pwm0 configuration bits 0 0 input mode 0 1 n-channel open-drain output mode ( 5 -volt load capacity) 1 0 push-pull output mode 1 1 pwm0 output mode (push-pull circuit type) .1 and .0 port 2.4 /pwm4 configuration bits 0 0 input mode 0 1 n-channel open-drain output mode ( 5 -volt load capacity) 1 0 push-pull output mode 1 1 pwm4 output mode (n-channel open-drain type)
s3c880a/f880a control registers 4 - 39 p2conl ? port 2 control register (low byte) e9h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .6 port 2.3 /pwm3 configuration bits 0 0 normal input mode 0 1 normal input mode 1 0 pwm3 output mode; n-channel, open-drain output mode with 5-volt load capacity 1 1 push-pull output mode .5 and .4 port 2.2 /pwm2 configuration bits 0 0 normal input mode 0 1 normal input mode 1 0 pwm2 output mode; n-channel, open-drain output mode with 5-volt load capacity 1 1 push-pull output mode .3 and .2 port 2.1 /pwm1 configuration bits 0 0 normal input mode 0 1 normal input mode 1 0 pwm1 output mode; n-channel, open-drain output mode with 5-volt load capacity 1 1 push-pull output mode .1 and .0 port 2.0 /pwm5 configuration bits 0 0 normal input mode 0 1 normal input mode 1 0 pwm5 output mode; n-channel, open-drain output mode with 5-volt load capacity 1 1 push-pull output mode
control registers s3c880a/f880a 4 - 40 p3conl ? port 3 control register (low byte) ebh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value ? ? ? ? 1 1 1 1 read/write ? ? ? ? r/w r/w r/w r/w addressing mode register addressing mode only .7 ? . 4 no effect .3 and .2 port 3.1/ adc1 configuration bits 0 0 input mode 0 1 adc input mode 1 0 input mode 1 1 n-channel, open-drain output mode with 5-volt load capacity .1 and .0 port 3.0/ adc0 configuration bits 0 0 input mode 0 1 adc input mode 1 0 input mode 1 1 n-channel, open-drain output mode with 5-volt load capacity
s3c880a/f880a control registers 4 - 41 pp ? register page pointer dfh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .4 destination register page selection bits 0 0 0 0 destination: page 0 0 0 0 1 destination: page 1 0 0 1 0 destination: page 2 0 0 1 1 not used for the s3c880a/f880a ? ? ? " 1 1 1 1 not used for the s3c880a/f880a .3 ? .0 source register page selection bits 0 0 0 0 source: page 0 0 0 0 1 source: page 1 0 0 1 0 source: page 2 0 0 1 1 not used for the s3c880a/f880a ? ? ? " 1 1 1 1 not used for the s3c880a/f880a
control registers s3c880a/f880a 4 - 42 pwmcon ? pwm control register f8h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 ? 0 0 read/write r/w r/w r/w r/w r/w ? r/w r/w addressing mode register addressing mode only . 4, . 7, and .6 3 -bit prescaler value for pwm counter input clock 0 0 0 non-divided input clock 0 0 1 divided-by-two input clock 0 1 0 divided-by-three input clock 0 1 1 divided-by-four input clock 1 0 0 divided-by- five input clock 1 0 1 divided-by- six input clock 1 1 0 divided-by- seven input clock 1 1 1 divided-by- eight input clock .5 pwm counter enable bit 0 stop pwm counter operation 1 start (or resume) pwm counter operation .3 capture a interrupt enable bit 0 disable capture a interrupt 1 enable capture a interrupt .2 not used for the s3c880a/f880a .1 and .0 capture a module control bits 0 0 disable capture a module 0 1 capture on falling edges only 1 0 capture on rising edges only 1 1 capture on both rising and falling edges
s3c880a/f880a control registers 4 - 43 rowcon ? osd row position control register f2h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .3 top margin display position control value (4 x tmg value of 0?31 dots) 0 0 0 0 0 top margin position = 0h 0 0 0 0 1 top margin position = 4h ? ? ? ? ? ? 1 1 1 1 1 top margin position = 124h .2 ? .0 inter-r ow spacing control value (0?7h) 0 0 0 no inter-row spacing 0 0 1 inter-row spacing = 1h ? ? ? ? ? ? 1 1 1 inter-row spacing = 7h note : to set top margin and inter-row spacing, separate decimal values must be calculated, converted to their binary equivalents, and then written to the row con register.
control registers s3c880a/f880a 4 - 44 rp0 ? register pointer 0 d6h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 1 1 0 0 0 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing mode only .7 ? .3 register pointer 0 address value register pointer 0 can independently point to one of the twenty four 8-byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp0 points to the address c0h in the register set 1, selecting the 8-byte working register slice c0h?c7h. .2 ? .0 not used for the s3c880a/f880a rp1 ? register pointer 1 d7h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 1 1 0 0 1 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing mode only .7 ? .3 register pointer 1 address value register pointer 1 can independently point to one of the twenty four 8-byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp1 points to the address c8h in the register set 1, selecting the 8-byte working register slice c8h?cfh. .2 ? .0 not used for the s3c880a/f880a.
s3c880a/f880a control registers 4 - 45 sph ? stack pointer (high byte) d8h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .0 stack pointer address (high byte) the high-byte stack pointer value is the upper 8 bits of the 16-bit stack pointer address (sp15?sp8). the lower byte of the stack pointer value is located in the register spl (d9h). the sp value is undefined after a reset. spl ? stack pointer (low byte) d9h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .0 stack pointer address (low byte) the low-byte stack pointer value is the lower 8 bits of the 16-bit stack pointer address (sp7?sp0). the upper byte of the stack pointer value is located in the r egister sph (d8h). the sp value is undefined after a reset.
control registers s3c880a/f880a 4 - 46 stcon ? stop control register f3 h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 ? .0 stop condition enable bits other set value stop condition disable (stop instruction is not available) 10100101 stop condition enable (stop instruction is available) note: when the stop control register, stcon, is set by '10100101b', stop instruction is available. the other value except '10100101b' make stop instruction not available. when stop condition is disabled, using "stop" instruction make state reset. once stop instruction is executed in state of stop instruction available, the state is changed to stop instruction not available.
s3c880a/f880a control registers 4 - 47 sym ? system mode register deh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 ? ? x x x 0 0 read/write r/w ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 tri-state external interface control bit (1) 0 normal operation (disable tri-state operation) 1 set external interface lines to high impedance (enable tri-state operation) .6?.5 not used for the s3c880a/f880a. .4 ? .2 fast interrupt level selection bits 0 0 0 level 0 (irq0) 0 0 1 level 1 (irq1) 0 1 0 level 2 (irq2) 0 1 1 level 3 (irq3) 1 0 0 level 4 (irq 4 ) 1 0 1 not used for s3c880a/f880a 1 1 0 level 6 (irq6) 1 1 1 level 7 (irq7) .1 fast interrupt enable bit 0 disable fast interrupt processing 1 enable fast interrupt processing .0 global interrupt enable bit ( 2 ) 0 disable global interrupt processing 1 enable global interrupt processing notes : 1. because the s3c880a/f880a microcontrollers do not have an external interface, bit 7 should always be "0". 2 . after a reset, the initialization routine must enable global interrupt processing by executing an ei instruction (and not by writing a "1" to sym.0).
control registers s3c880a/f880a 4 - 48 tacon ? timer a control register f2h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 0 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? addressing mode register addressing mode only .7 ? .4 4-bit prescaler for timer a clock input 0 0 0 0 divide input by 1 (non-divided) 0 0 0 1 divide input by 2 ? ? ? ? ? ? 1 1 1 1 divide input by 16 .3 timer a clock source selection bit 0 cpu clock divided by 1000 1 n on-divided cpu clock .2 timer a interrupt enable bit 0 disable interrupt 1 enable interrupt .1 timer a interrupt pending bit 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 i nterrupt is pending (when read) 1 no effect (when write) .0 no t used for the s3c880a/f880a
s3c880a/f880a control registers 4 - 49 t0con ? timer 0 control register d2h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value 0 0 0 0 0 ? 0 0 read/write r/w r/w r/w r/w r/w ? r/w r/w addressing mode register addressing mode only .7 and .6 t0 input clock selection bits 0 0 f osc /4096 0 1 f osc /256 1 0 f osc /8 1 1 external clock (t0clk) .5 and .4 t0 operating mode selection bits 0 0 interval mode 0 1 pwm mode 1 0 pwm mode 1 1 pwm mode .3 t0 counter clear bit 0 no effect 1 clear the t0 counter (when write) .2 no effect .1 t0 interrupt enable bit 0 disable t0 interrupt 1 enable t0 interrupt .0 t0 interrupt pending bit 0 no timer 0 interrupt pending (when read) 0 clear timer 0 pending bit (when write) 1 timer 0 interrupt is pending (when read) 1 no effect (when write)
control registers s3c880a/f880a 4 - 50 vsbc on ? v-sync blank control register f7 h set 1 , bank1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 nreset value ? ? ? 0 1 0 0 1 read/write ? ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 and .5 not used for the s3c880a/f880a . 4? . 0 v-sync blank time control bits: 0 0 0 0 0 9 horizontal sync ? ? ? 0 1 0 0 1 9 horizontal sync 0 1 0 1 0 10 horizontal sync 0 1 0 1 1 11 horizontal sync ? ? ? ? ? ? 1 1 1 1 1 31 horizontal sync
s3c880a/f880a interrupt structure 5 - 1 5 interrupt structure overview the sam87 interrupt structure has three basic components: levels, vectors, and sources. the cpu recognizes 8 interrupt levels and supports up to 128 interrupt vectors. when a specific interrupt level has more than one vector address, the vector priorities are established in hardware. each vector can have one or more interrupt sources. levels levels provide the highest-level method of interrupt priority assignment and recognition. all peripherals and i/o blocks can issue interrupt requests. in other words, peripheral and i/o operations are interrupt-driven. there are eight interrupt levels: irq0?irq7. each interrupt level directly corresponds to an interrupt request number (irqn). the total number of interrupt levels used in the interrupt structure varies from device to device. for the s3c880a/f880a microcontrollers, seven levels are recognized: irq0?irq 4 , irq6, and irq7. the interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. they are simply identifiers for the interrupt levels that are recognized by the cpu (irq0?irq7). the relative priority of different interrupt levels is determined by settings in the interrupt priority register, ipr. interrupt logic controlled by the ipr settings lets you define additional priority relationship for specific interrupt levels. vectors each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. the maximum number of vectors that can be supported for a given level is 128. (the actual number of vectors used for the s3c8 -series microcontrollers is always much smaller.) if an interrupt level has more than one vector address, the vector priorities are set in hardware. the s3c880a/f880a have 9 vectors, one corresponding to each of the 9 possible sources. sources a source is any peripheral that generates an interrupt. a source can be an external pin or a counter overflow, for example. each vector can have several interrupt sources. in the s3c880a/f880a interrupt structure, each source has its own vector address. when a service routine starts, the respective pending bit is either cleared automatically by hardware or "manually" by the program software. the characteristics of the source's pending mechanism determine which method is used to clear its pending bit. interrupt types the three components of the sam87 interrupt structure described above ? levels, vectors, and sources ? are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. there are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. the types differ in the number of vectors and interrupt sources assigned to each level (see figure 5 - 1): type 1: one level (irqn) + one vector (v 1 ) + one source (s 1 ) type 2: one level (irqn) + one vector (v 1 ) + multiple sources (s 1 ? s n ) type 3: one level (irqn) + multiple vectors (v 1 ? v n ) + multiple sources (s 1 ? s n , s n+1 ? s n+m ) in the s3c880a/f880a interrupt structure, only interrupt types 1 and 3 are implemented.
interrupt structure s3c880a/f880a 5 - 2 vectors sources levels s 1 v 1 s 2 type 2: irqn s 3 s n v 1 s 1 v 2 s 2 type 3: irqn v 3 s 3 v 1 s 1 type 1: irqn v n s n + 1 s n s n + 2 s n + m notes: 1. the number of s n and v n value is expandable. 2. in the S3F880A implementation, only interrupt types 1 and 3 are used. figure 5 - 1. s3c8 -series interrupt types s3c880a/f880a interrupt structure the s3c880a/f880a microcontrollers have 9 standard interrupt sources. nine different vector addresses are used to support these interrupt sources. s even of the eight available levels are used for the interrupt structure: irq0?irq 4 , irq6, and irq7. the device-specific interrupt structure is shown in figure 5 - 2. when multiple interrupt levels are active, the interrupt priority register (ipr) determines the order in which contending interrupts are to be serviced. if multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first. (the relative priorities of multiple interrupts within a single level are hardwired.) when an interrupt request is granted, interrupt processing starts: s ubsequent interrupts are disabled and the program counter value and status flags are pushed to stack. the starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed.
s3c880a/f880a interrupt structure 5 - 3 0 notes: 1. the interrupt level irq5 is not used in the S3F880A interrupt structure. 2. for interrupt levels with two or more vectors, the lowest vector address usually has the highest priority. for example, c0h has higher priority (0) than c2h (1) within the level irq1. these priorities (see numbers) are hardwired. 3. the interrupt names in the 'identifier' column are used in this documentation to refer to specific interrupts, as distinguished from the interrupt source name or the pin at which an external interrupt request arrives. vectors sources levels c0h p1.0 external interrupt irq1 c2h p1.1 external interrupt reset h/w h/w osd row interrupt irq2 c4h 02h capture a (8-bit) irq3 h/w timer 0 interrupt (match) irq0 fch c6h p1.2 external interrupt irq4 c8h p1.3 external interrupt h/w h/w timer a irq6 beh d4h v-sync irq7 s/w identifier t0int p10int capa p12int p13int vsync p11int rowint taint s/w s/w s/w 1 0 1 figure 5 - 2. s3c880a/f880a interrupt structure
interrupt structure s3c880a/f880a 5 - 4 interrupt vector addresses interrupt vector addresses for the s3c880a/f880a are stored in the first 256 bytes of the rom. the reset address is 0100h. vectors for all interrupt levels are stored in the vector address area (0h?ffh). unused rom in the range 00h?ffh can be used as program memory locations. you must be careful, however, not to overwrite interrupt vector addresses stored in this area. 45,151 0 (decimal) 256 255 interrupt vector address area addressable program memory (rom) area 100h ffh bfffh (for S3F880A) (hex) nreset address figure 5 - 3. rom vector address area
s3c880a/f880a interrupt structure 5 - 5 table 5 - 1. s3c880a/f880a interrupt vectors vector address interrupt source request reset/clear decimal value hex value interrupt level priority in level h/w s/w 252 fch timer 0 (match) irq0 ? ? 212 d4h v-sync irq7 ? ? 200 c8h p1.3 external interrupt irq4 1 ? 198 c6h p1.2 external interrupt 0 ? 196 c4h osd row interrupt irq2 ? ? 194 c2h p 1.1 external interrupt irq1 1 ? 192 c0h p 1.0 external interrupt 0 ? 190 beh timer a irq6 ? ? 2 02h capture a (8-bit) irq3 ? ? notes : 1. interrupt priorities are identified in inverse order: '0' is the highest priority, '1' is the next highest, and so on. 2. if two or more inte rrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. (the priorities within a level are hardwired) for example, in the interrupt level irq1, the higher-priority interrupt vector is the p 1.0 external interrupt, vector c0h; the lower-priority interrupt within that level is the p 1.1 external interrupt, vector c2h.
interrupt structure s3c880a/f880a 5 - 6 enable/disable interrupt instructions (ei, di) the enable interrupts (ei) instruction globally enables the interrupt structure. all interrupts are serviced as they occur, and according to established priorities. the system initialization routine that is executed following a reset must always contain an ei instruction (assuming one or more interrupts are used in the application). during the normal operation, you can execute the di (disable interrupt) instruction at any time to globally disable interrupt processing. the ei and di instructions change the value of bit 0 in the sym register. although you can manipulate sym.0 directly to enable or disable interrupts, we recommend that you use the ei and di instructions instead. system-level interrupt control registers in addition to the control registers for specific interrupt sources, four system-level control registers control interrupt processing: ? each interrupt level is enabled or disabled (masked) by bit settings in the interrupt mask register (imr). ? relative priorities of interrupt levels are controlled by the interrupt priority register (ipr). ? the interrupt request register (irq) contains interrupt pending flags for each level. ? the system mode register (sym) dynamically enables or disables global interrupt processing. sym settings also enable fast interrupts and control external interface, if implemented. table 5 - 2. interrupt control register overview control register id r/w function description system mode register sym r/w global interrupt processing enable and disable, fast interrupt processing. interrupt mask register imr r/w bit settings in the imr register enable and disable interrupt processing for each of the seven recognized interrupt levels, irq0?irq 4 , irq6, and irq7. interrupt priority register ipr r/w controls the relative processing priorities of the interrupt levels. for the s3c880a/f880a , the seven levels are organized into three groups: a, b, and c. group a includes irq0 and irq1, group b is irq2 , irq3, and irq 4 , and group c is irq6 and irq7. interrupt request register irq r this register contains a request pending bit for each interrupt level.
s3c880a/f880a interrupt structure 5 - 7 interrupt processing control points interrupt processing can therefore be controlled in two ways: either globally, or by specific interrupt level and source. the system-level control points in the interrupt structure are therefore: ? global interrupt enable and disable (by ei and di instructions or by direct manipulation of sym.0 ) ? interrupt level enable and disable settings (imr register) ? interrupt level priority settings (ipr register) ? interrupt source enable and disable settings in the corresponding peripheral control register(s) note when writing an interrupt service routine, be sure that it properly manages the register pointer values (rp0 and rp1). interrupt mask register interrupt priority register global interrupt control (ei, di or sym.0 manipulation) vector interrupt cycle source interrupt source interrupts enable interrupt request register (read-only) s r q reset "ei" instruction execution interrupt pending register polling cycle note: in the S3F880A microcontrollers, only seven interrupt levels (irq0-irq4, irq6, and irq7) are recognized by the cpu. figure 5 - 4. interrupt function diagram
interrupt structure s3c880a/f880a 5 - 8 peripheral interrupt control registers for each interrupt source there is a corresponding peripheral control register (or registers) that control s the interrupts generated by th e peripheral. these registers and their locations are listed in table 5 - 3. table 5 - 3. interrupt source control registers interrupt source interrupt level control register register location timer 0 (match) irq0 t0con set 1, d2h p 1.0 external interrupt irq1 p 1 con l set 1, bank 0, e 7 h p1.1 external interrupt osd row interrupt irq2 htcon set 1, bank 1 , e 6 h capture a (8-bit) irq3 pwmcon set 1, bank 0, f8h p1.2 external interrupt irq4 p1conl set 1, bank 0, e7h p1.3 external interrupt timer a irq6 tacon set 1, bank 0, f2h v-sync irq7 htcon set 1, bank 1, f6h
s3c880a/f880a interrupt structure 5 - 9 system mode register (sym) the system mode register, sym (deh, set 1), is used to enable and disable interrupt processing and control fast interrupt processing. sym.0 is the enable and disable bit for global interrupt processing. sym.1?sym.4 control fast interrupt processing: sym.1 is the enable bit; sym.2?sym.4 are the fast interrupt level selection bits. sym.7 is the enable bit for the tri- state external memory interface (not implemented in the s3c880a/f880a ). a reset clears s ym.0, sym.1, and sym.7 to "0"; other bit values are undetermined. the instructions ei and di enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the sym register. an enable interrupt (ei) instruction must be included in the initialization routine, which follows a reset operation, in order to enable interrupt processing. although you can manipulate sym.0 directly to enable and disable interrupts during the normal operation, we recommend using the ei and di instructions for this purpose. system mode register (sym) dfh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb fast interrupt level selection bits: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 irq0 irq1 irq2 irq3 irq4 not used irq6 irq7 global interrupt enable bit: 0 = disable all interrupts 1 = enable all interrupts fast interrupt enable bit: 0 = disable fast interrupts 1 = enable fast interrupts not used external interface tri-state enable bit: 0 = normal operation (tri-state disabled) 1 = high inpendence (tri-state disabled) note: the external interface is not implemented for the S3F880A microcontroller. figure 5 - 5. system mode register (sym)
interrupt structure s3c880a/f880a 5 - 10 interrupt mask register (imr) the interrupt mask register (imr) is used to enable or disable interrupt processing for each of the s even interrupt levels used in the s3c880a/f880a interrupt structure, irq0?irq 4 , irq6, and irq7. after a reset, all the imr register values are undetermined. each imr bit corresponds to a specific interrupt level: bit 1 to irq1, bit 2 to irq2, and so on. when the imr bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). when you set a level's imr bit to "1", interrupt processing for the level is enabled (not masked). the imr register is mapped to the register location ddh in set 1. bit values can be read and written by instructions using register addressing mode. interrupt mask register (imr) ddh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb irq1 irq3 irq4 not used irq6 irq7 irq0 interrupt level enable bits: 0 = disable interrupt level 1 = enable interrupt level irq2 figure 5 - 6. interrupt mask register (imr)
s3c880a/f880a interrupt structure 5 - 11 interrupt priority register (ipr) the interrupt priority register, ipr, is used to set the relative priorities of the s even interrupt levels used in the s3c880a/f880a interrupt structure. the ipr register is mapped to the register location ffh in set 1, bank 0. after a reset, the ipr register values are undetermined. if more than one interrupt source is active, the source with the highest priority level is serviced first. if both sources belong to the same interrupt level, the source with the lowest vector address usually has priority. (this priority is hardwired.) in order to define the relative priorities of interrupt levels, they are organized into groups and subgroups by the interrupt logic. three interrupt groups are defined for the ipr logic (see figure 5 - 7). these groups and subgroups are used only for ipr register priority definitions: group a irq0, irq1 group b irq2, irq3 , and irq4 group c irq6, irq7 bits 7, 4, and 1 of the ipr register control the relative priority of interrupt groups a, b, and c. for example, the setting '001b' would select the group relationship b > c > a, and '101b' would select c > b > a. the functions of other ipr bit settings are as follows: ? ipr.0 controls the relative priority setting of irq0 and irq1 interrupts. ? ipr.2 controls interrupt group b. ? interrupt group b has a subgroup to provide an additional priority relationship among interrupt levels 2, 3, and 4. ipr.3 defines possible subgroup b relationship. ? ipr.6 controls the relative priorities of group c interrupts. interrupt priority register (ipr) feh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb group a 0 = irq0 > irq1 1 = irq1 > irq0 subgroup b 0 = irq3 > irq4 1 = irq4 > irq3 not used group c 0 = irq6 > irq7 1 = irq7 > irq6 group b 0 = irq2 > (irq3, irq4) 1 = (irq3, irq4) > irq2 group priority: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 = undefined = b > c > a = a > b > c = b > a > c = c > a > b = c > b > a = a > c > b = undefined d7 d4 d1 figure 5 - 7. interrupt priority register (ipr)
interrupt structure s3c880a/f880a 5 - 12 interrupt request register (irq) bit values in the interrupt request register, irq, are polled to determine interrupt request status for the seven interrupt levels in the s3c880a/f880a interrupt structure (irq0?irq 4 , irq6, and irq7). each bit corresponds to the interrupt level of the same number: bit 0 to irq0, bit 1 to irq1, and so on. a "0" indicates that no interrupt is requested and a "1" indicates that an interrupt is requested for that level. the irq register is mapped to the register location dch in set 1. irq bit values are read-only addressable using register addressing mode. you can read (test) the contents of the irq register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. after a reset, the irq register is cleared to 00h. irq register values can be polled even if a di instruction has been executed. if an interrupt occurs while the interrupt structure is disabled, it will not be serviced. but the interrupt request can still be detected by polling irq values. this can be useful in order to determine which events occurred while the interrupt structure was disabled. interrupt request register (irq) dch, set 1, read-only .7 .6 .5 .4 .3 .2 .1 .0 msb lsb irq1 irq2 irq3 irq4 not used for the S3F880A. irq6 irq7 irq0 interrupt level request pending bits: 0 = interrupt level is not pending 1 = interrupt level is pending figure 5 - 8. interrupt request register (irq)
s3c880a/f880a interrupt structure 5 - 13 interrupt pending function types overview there are two types of interrupt pending bits : o ne is the type that automatically cleared by hardware after the interrupt service routine is acknowledged and executed ; t he other is the one that must be cleared by the application program's interrupt service routine. each interrupt level has a corresponding interrupt request bit in the irq register that the cpu polls for interrupt requests. pending bits cleared automatically by hardware for interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. it then issues an irq pulse to tell the cpu that an interrupt is waiting to be serviced. the cpu acknowledges the interrupt source, executes the service routine, and clears the pending bit to "0". this type of pending bit is not mapped and cannot, therefore, be read or written by software. in the s3c880a/f880a interrupt structure, the p 1.0, p1.1, p1.2 and p1.3 external interrupts, and the capture a interrupt belong to this category of interrupts whose pending conditions are cleared automatically by hardware. pending bits cleared by the service routine the second type of pending bit must be cleared by program software. the service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (iret) occurs. to do this, a "0" must be written to the pending bit location in the corresponding mode or control register. pending conditions for the timer 0 match interrupt, the timer a interrupt, the osd row interrupt and the v-sync interrupt must be cleared by the application's service routines.
interrupt structure s3c880a/f880a 5 - 14 interrupt source polling sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request bit to "1". 2. the cpu polling procedure identifies a pending condition for that source. 3. the cpu checks the source's interrupt level. 4. the cpu generates an interrupt acknowledge signal. 5. interr upt logic determines the i nterrupt's vector address. 6. the service routine starts and the source's pending flag is cleared to "0" (either by hardware or by software). 7. the cpu continues polling for interrupt requests. interrupt service routines before an interrupt request is serviced, the following conditions must be met: ? interrupt processing must be enabled (ei, sym.0 = "1") ? interrupt level must be enabled (imr register) ? interrupt level must have the highes t priority if more than one level is currently requesting service ? interrupt must be enabled at the interrupt's source (peripheral control register) if all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the interrupt enable bit in the sym register (sym.0) to disable all subsequent interrupts. 2. save the program counter and sta tus flags to stack. 3. branch to the interrupt vector to fetch the service routine's address. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, an interrupt return instruction (iret) occurs. the iret restores the pc and status flags and sets sym.0 to "1", allowing the cpu to process the next interrupt request.
s3c880a/f880a interrupt structure 5 - 15 generating interrupt vector addresses the interrupt vector area in the rom contains the addresses of the interrupt service routine that corresponds to each level in the interrupt structure. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to stack. 2. push the program counter's high-byte value to stack. 3. push the flags register values to stack. 4. fetch the service routine's high-byte address from the vector address. 5. fetch the service routine's low-byte address from the vector address. 6. branch to the service routine specified by the 16-bit vector a ddress. note a 16-bit vector address always begins at an even-numbered rom location from 00h?ffh. nesting of vectored interrupts you can nest a higher priority interrupt request while a lower priority request is being serviced. to do this, you must follow these steps: 1. push the current 8-bit interrupt mask register (imr) value to the stack (push imr). 2. load the imr register with a new mask to enable the higher priority interrupt only. 3. execute an ei instru ction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. when the lower-priority interrupt service routine ends, re turn the imr to its original value by re storing the previous mask from the stack (pop imr). 5. execute an iret. depending on the application, you may be able to simplify this procedure to some extent. instruction pointer (ip) the instruction pointer (ip) is used by all the s3c8 -series microcontrollers to control optional high-speed interrupt processing called fast interrupts . the ip consists of the register pair , dah and dbh. the ip register names are iph (high byte, ip15?ip8) and ipl (low byte, ip7?ip0).
interrupt structure s3c880a/f880a 5 - 16 fast interrupt processing the feature called fast interrupt processing lets designated interrupts be completed in approximately six clock cycles instead of the usual 22 clock cycles. bit 1 of the system mode register, sym.1, enables fast interrupt processing while sym.2?sym.4 are used to select a specific level for fast processing. two other system registers support fast interrupts: ? the instruction pointer (ip) holds the starting address of the service routine (and is later used to swap the program counter values), and ? when a fast interrupt occurs, the contents of the flags register is stored in an unmapped, dedicated register called flags' (flags prime). note for the s3c880a/f880a microcontroller s , the service routine for any one of the s even interrupt levels (irq0? irq 4 , irq6, or irq7) can be designated as a fast interrupt. procedure for initiating fast interrupts to initiate fast interrupt processing, follow these steps: 1. load the start address of the service routine into the instruction pointer. 2. load the level number into the fast interrupt select field. 3. write a "1" to the fast interrupt enable bit in the sym register. fast interrupt service routine when an interrupt occurs in the level selected for fast interrupt processing, the following events occur: 1. the contents of the instruction pointer and the pc are swapped. 2. the flags register values are written to the dedicated flags' register. 3. the fast interrupt status bit in the flags register is set. 4. the interrupt is serviced. 5. assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and pc values are swapped back. 6. the content of flags' (flags prime) is copied automatically back into the flags register. 7. the fast interrupt status bit in flags is cleared automatically. programming guidelines remember that the only way to enable or disable a fast interrupt is to set or clear the fast interrupt enable bit in the sym register (sym.1), respectively. executing an ei or di instruction affects only normal interrupt processing. also, if you use fast interrupts, remember to load the ip with a new start address when the fast interrupt service routine ends. (please refer to the programming tip on page 5?17 for an example.)
s3c880a/f880a interrupt structure 5 - 17 f programming tip ? programming level irq0 as a fast interrupt this example shows you how to program fast interrupt processing for a select interrupt level ? in this case, for the timer 0 (capture) interrupt, int0: ? ? ? ld t0con,#52h ; enable t0 interrupt ; select f osc /256 as t0 clock source ldw iph,#t0_int ; iph ? high byte of interrupt service routine ; ipl ? low byte of interrupt service routine ld sym,#02h ; enable fast interrup t processing ; select irq0 for fast service ei ; enable interrupts ? ? ? fast_ret: ; ip ? address of t0_int (again) t0_int: ? ? ? (fast service routine executes) ? ? ? ld t0con,#52h ; clear t0int interrupt pending bit jp t,fast_ret
interrupt structure s3c880a/f880a 5 - 18 notes
s3c880a/f880a sam8 instruction set 6 - 1 6 sam8 instruction set overview the sam8 instruction set is designed to support a large register file. it includes a full complement of 8-bit arithmetic and logic operations, including multi plying and divid ing . there are 78 instructions. no special i/o instructions are necessary because i/o control and data registers are mapped directly into the register file. decimal adjustment is included in binary-coded decimal (bcd) operations. 16-bit word data can be incremented and decremented. flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the sam8 instruction set. data types the sam8 cpu performs operations on bits, bytes, bcd digits, and two-byte words. bits in the register file can be set, cleared, complemented, and tested. bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. register addressing to access an individual register, an 8-bit address in the range 0 ? 255 or the 4-bit address of a working register is specified. paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. for detailed information about register addressing, please refer to chapter 2, "address spaces." addressing modes there are seven addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), immediate (im), and indirect (ia). for detailed descriptions of these addressing modes, please refer to chapter 3, "addressing modes."
sam8 instruction set s3c880a/f880a 6 - 2 table 6 - 1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst,src load ldb dst,src load bit lde dst,src load external data memory ldc dst,src load program memory lded dst,src load external data memory and decrement ldcd dst,src load program memory and decrement ldei dst,src load external data memory and increment ldci dst,src load program memory and increment ldepd dst,src load external data memory with pre-decrement ldcpd dst,src load program memory with pre-decrement ldepi dst,src load external data memory with pre-increment ldcpi dst,src load program memory with pre-increment ldw dst,src load word pop dst pop from stack popud dst,src pop user stack (decrementing) popui dst,src pop user stack (incrementing) push src push to stack pushud dst,src push user stack (decrementing) pushui dst,src push user stack (incrementing)
s3c880a/f880a sam8 instruction set 6 - 3 table 6 - 1. instruction group summary (continued) mnemonic operands instruction arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare da dst decimal adjust dec dst decrement decw dst decrement word div dst,src divide inc dst increment incw dst increment word mult dst,src multiply sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or
sam8 instruction set s3c880a/f880a 6 - 4 table 6 - 1. instruction group summary (continued) mnemonic operands instruction program control instructions btjrf dst,src bit test and jump relative on false btjrt dst,src bit test and jump relative on true call dst call procedure cpije dst,src compare, increment and jump on equal cpijne dst,src compare, increment and jump on non-equal djnz r,dst decrement register and jump on non-zero enter enter exit exit iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code next next ret return wfi wait for interrupt bit manipulation instructions band dst,src bit and bcp dst,src bit compare bitc dst bit complement bitr dst bit reset bits dst bit set bor dst,src bit or bxor dst,src bit xor tcm dst,src test complement under mask tm dst,src test under mask
s3c880a/f880a sam8 instruction set 6 - 5 table 6 - 1. instruction group summary (concluded) mnemonic operands instruction rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic swap dst swap nibbles cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag sb0 set bank 0 sb1 set bank 1 scf set carry flag srp src set register pointers srp0 src set register pointer 0 srp1 src set register pointer 1 stop enter stop mode
sam8 instruction set s3c880a/f880a 6 - 6 flags register (flags) the flags register flags contains eight bits that describe the current status of the cpu operations. four of these bits, flags.4 ? flags.7, can be tested and used with conditional jump instructions; two others flags.2 and flags.3 are used for bcd arithmetic. the flags register also contains a bit to indicate the status of fast interrupt processing (flags.1) and a bank address status bit (flags.0) to indicate whether bank 0 or bank 1 is being addressed. flags is located in the system control register area of set 1 (d5h). flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then simultaneously, two writes will occur to the flags register, producing an unpredictable result. system flags register (flags) d5h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb bank address status flag (ba) first interrupt status flag (fis) half-carry flag (h) decimal adjust flag (d) overflow (v) sign flag (s) zero flag (z) carry flag (c) figure 6 - 1. system flags register (flags)
s3c880a/f880a sam8 instruction set 6 - 7 flag descriptions c carry flag (flags.7) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag. z zero flag (flags.6) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. for operations that test register bits, and for shift and rotate operations, the z flag is set to "1" if the result is logic zero. s sign flag (flags.5) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. v overflow flag (flags.4) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is also cleared to "0" following logic operations. d decimal adjust flag (flags.3) the da bit is used to specify what type of instruction was executed last during bcd operations, so that a subsequent decimal adjust operation can execute correctly. the da bit is not usually accessed by programmers, and cannot be used as a test condition. h half-carry flag (flags.2) the h bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. it is used by the decimal adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (bcd) result. the h flag is seldom accessed directly by a program. fis fast interrupt status flag (flags.1) the fis bit is set during a fast interrupt cycle and reset during the iret following interrupt servicing. when set, it inhibits all interrupts and causes the fast interrupt return to be executed when the iret instruction is executed. ba bank address flag (flags.0) the ba flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. the ba flag is cleared to "0" (select bank 0) when you execute the sb0 instruction and is set to "1" (select bank 1) when you execute the sb1 instruction.
sam8 instruction set s3c880a/f880a 6 - 8 instruction set notation table 6 - 2. flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag d decimal-adjust flag h half-carry flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6 - 3. instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter ip instruction pointer flags flags register (d5h) rp register pointer # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
s3c880a/f880a sam8 instruction set 6 - 9 table 6 - 4. instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6 - 6. r working register only rn (n = 0?15) rb bit (b) of working register rn.b (n = 0?15, b = 0?7) r0 bit 0 (lsb) of working register rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn (reg = 0?255, n = 0?15) rb bit 'b' of register or working register reg.b (reg = 0?255, b = 0?7) rr register pair or working register pair reg or rrp (reg = 0?254, even number only, where p = 0, 2, ..., 14) ia indirect addressing mode addr (addr = 0?254, even number only) ir indirect working register only @rn (n = 0?15) ir indirect register or indirect working register @rn or @reg (reg = 0?255, n = 0?15) irr indirect working register pair only @rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @rrp or @reg (reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode #reg[rn] (reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode #addr[rrp] (addr = range ?128 to +127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode #addr [rrp] (addr = range 0?65535, where p = 0, 2, ..., 14) da direct addressing mode addr (addr = range 0?65535) ra relative addressing mode addr (addr = number in the range +127 to ?128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255) iml immediate (long) addressing mode #data (data = range 0?65535)
sam8 instruction set s3c880a/f880a 6 - 10 table 6 - 5. opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im bor r0?rb p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im bcp r1.b, r2 p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im bxor r0?rb e 3 jp irr1 srp/0/1 im sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im btjr r2.b, ra r 4 da r1 da ir1 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im ldb r0?rb 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im bitc r1.b n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im band r0?rb i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im bit r1.b b 8 decw rr1 decw ir1 pushud ir1,r2 pushui ir1,r2 mult r2,rr1 mult ir2,rr1 mult im,rr1 ld r1, x, r2 b 9 rl r1 rl ir1 popud ir2,r1 popui ir2,r1 div r2,rr1 div ir2,rr1 div im,rr1 ld r2, x, r1 l a incw rr1 incw ir1 cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 cpije ir,r2,ra ldc r1,irr2 ldw rr2,rr1 ldw ir2,rr1 ldw rr1,iml ld r1, ir2 h d sra r1 sra ir1 cpijne irr,r2,ra ldc r2,irr1 call ia1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld ir2,r1 ld r1,im ldc r1, irr2, xs x f swap r1 swap ir1 ldcpd r2,irr1 ldcpi r2,irr1 call irr1 ld r2,ir1 call da1 ldc r2, irr1, xs
s3c880a/f880a sam8 instruction set 6 - 11 table 6 - 5. opcode quick reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 next p 1 enter p 2 exit e 3 wfi r 4 sb0 5 sb1 n 6 idle i 7 stop b 8 di b 9 ei l a ret e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 nop
sam8 instruction set s3c880a/f880a 6 - 12 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6 - 6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6 - 6. condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (1) c carry c = 1 1111 (1) nc no carry c = 0 0110 (1) z zero z = 1 1110 (1) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (1) eq equal z = 1 1110 (1) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (1) uge unsigned greater than or equal c = 0 0111 (1) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. it indicate s condition codes that are related to two different mnemonics but which test the same flag. for example, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used; after a cp instruction, however, eq would probably be used. 2. for operations involving unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
s3c880a/f880a sam8 instruction set 6 - 13 instruction descriptions this chapter contains detailed information and programming examples for each instruction in the sam8 instruction set. information is arranged in a consistent format for improved readability and fast referencing. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? specific flag settings affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming exam ple(s) explaining how to use the instruction
sam8 instruction set s3c880a/f880a 6 - 14 adc ? add w ith carry adc dst,src operation: dst ? dst + src + c the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. in multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 6 12 r r 13 r lr opc src dst 3 10 14 r r 15 r ir opc dst src 3 10 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 ? r1 = 14h, r2 = 03h adc r1,@r2 ? r1 = 1bh, r2 = 03h adc 01h,02h ? register 01h = 24h, register 02h = 03h adc 01h,@02h ? register 01h = 2bh, register 02h = 03h adc 01h,#11h ? register 01h = 32h in the first example, the destination register r1 contains the value 10h, the carry flag is set to "1", and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in the register r1.
s3c880a/f880a sam8 instruction set 6 - 15 add ? add add dst,src operation: dst ? dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if a carry from the low-order nibble occurred. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 6 02 r r 03 r lr opc src dst 3 10 04 r r 05 r ir opc dst src 3 10 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 ? r1 = 15h, r2 = 03h add r1,@r2 ? r1 = 1ch, r2 = 03h add 01h,02h ? register 01h = 24h, register 02h = 03h add 01h,@02h ? register 01h = 2bh, register 02h = 03h add 01h,#25h ? register 0 1h = 46h in the first example, the destination working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in the register r1.
sam8 instruction set s3c880a/f880a 6 - 16 and ? logical and and dst,src operation: dst ? dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 6 52 r r 53 r lr opc src dst 3 10 54 r r 55 r ir opc dst src 3 10 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: and r1,r2 ? r1 = 02h, r2 = 03h and r1,@r2 ? r1 = 02h, r2 = 03h and 01h,02h ? register 01h = 01h, register 02h = 03h and 01h,@02h ? register 01h = 00h, register 02h = 03h and 01h,#25h ? register 01h = 21h in the first example, the destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in the register r1.
s3c880a/f880a sam8 instruction set 6 - 17 band ? bit and band dst,src.b band dst.b,src operation: dst(0) ? dst(0) and src(b) or dst(b) ? dst(b) and src(0) the specified bit of the source (or the destination) is logically anded with the zero bit (lsb) of the destination (or source). the resultant bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 10 67 r0 rb opc src | b | 1 dst 3 10 67 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h and register 01h = 05h: band r1,01h.1 ? r1 = 05h, register 01h = 05h band 01h.1,r1 ? register 01h = 05h, r1 = 07h in the first example, the source register 01h contains the value 05h (00000101b) and the destination working register r1 contains 07h (00000111b). the statement "band r1,01h.1" ands the bit 1 value of the source register ("0") with the bit 0 value of the register r1 (destination), leaving the value 0525h (00000101b) in the register r1.
sam8 instruction set s3c880a/f880a 6 - 18 bcp ? bit compare bcp dst,src.b operation: dst(0) ? src(b) the specified bit of the source is compared to (subtracted from) bit zero (lsb) of the destination. the zero flag is set if the bits are the same; otherwise it is cleared. the contents of both operands are unaffected by the comparison. flags: c: unaffected. z: set if the two bits are the same; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 10 17 r0 rb note : in th e second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h and register 01h = 01h: bcp r1,01h.1 ? r1 = 07h, register 01h = 01h if the destination working register r1 contains the value 07h (00000111b) and the source register 01h contains the value 01h (00000001b), the statement "bcp r1,01h.1" compares bit one of the source register (01h) and bit zero of the destination register (r1). because the bit values are not identical, the zero flag bit (z) is cleared in the flags register (0d5h).
s3c880a/f880a sam8 instruction set 6 - 19 bitc ? bit complement bitc dst.b operation: dst(b) ? not dst(b) this instruction complements the specified bit within the destination without affecting any other bit in the destination. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 8 57 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h bitc r1.1 ? r1 = 05h if the working register r1 contains the value 07h (00000111b), the statement "bitc r1.1" complements bit one of the destination , leaving the value 05h (00000101b) in the register r1. because the result of the complement is not "0", the zero flag (z) in the flags register (0d5h) is cleared.
sam8 instruction set s3c880a/f880a 6 - 20 bitr ? bit reset bitr dst.b operation: dst(b) ? 0 the bitr instruction clears the specified bit within the destination without affecting any other bit in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 8 77 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bitr r1.1 ? r1 = 05h if the value of the working register r1 is 07h (00000111b), the statement "bitr r1.1" clears bit one of the destination register r1, leaving the value 05h (00000101b).
s3c880a/f880a sam8 instruction set 6 - 21 bits ? bit set bits dst.b operation: dst(b) ? 1 the bits instruction sets the specified bit within the destination without affecting any other bit in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 1 2 8 77 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bits r1.3 ? r1 = 0fh if the working register r1 contains the value 07h (00000111b), the statement "bits r1.3" sets bit three of the destination register r1 to "1", leaving the value 0fh (00001111b).
sam8 instruction set s3c880a/f880a 6 - 22 bor ? bit or bor dst,src.b bor dst.b,src operation: dst(0) ? dst(0) or src(b) or dst(b) ? dst(b) or src(0) the specified bit of the source (or destination) is logically ored with bit zero (lsb) of the destination (or source). the resulting bit value is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 10 07 r0 rb opc src | b | 1 dst 3 10 07 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit. examples: given: r1 = 07h and register 01h = 03h: bor r1, 01h.1 ? r1 = 07h, register 01h = 03h bor 01h.2, r1 ? register 01h = 07h, r1 = 07h in the first example, the destination working register r1 contains the value 07h (00000111b) and the source register 01h the value 03h (00000011b). the statement "bor r1,01h.1" logically ors bit one of the register 01h (source) with bit zero of r1 (destination). this leaves the same value (07h) in the working register r1. in the second example, the destination register 01h contains the value 03h (00000011b) and the source working register r1 the value 07h (00000111b). the statement "bor 01h.2,r1" logically ors bit two of the register 01h (destination) with bit zero of r1 (source). this leaves the value 07h in the register 01h.
s3c880a/f880a sam8 instruction set 6 - 23 btjrf ? bit test, jump relative on false btjrf dst,src.b operation: if src(b) is a "0", then pc ? pc + dst the specified bit within the source operand is tested. if it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the pc; otherwise, the instruction following the btjrf instruction is executed. flags: no flags are affected. format: (1) bytes cycles opcode (hex) addr mode dst src opc src | b | 0 dst 3 16/18 (2) 37 ra rb notes: 1. in the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. 2. execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 07h: btjrf skip,r1.3 ? pc jumps to skip location if the working register r1 contains the value 07h (00000111b), the statement "btjrf skip,r1.3" tests bit 3. because it is "0", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
sam8 instruction set s3c880a/f880a 6 - 24 btjrt ? bit test, jump relative on true btjrt dst,src.b operation: if src(b) is a "1", then pc ? pc + dst the specified bit within the source operand is tested. if it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the pc; otherwise, the instruction following the btjrt instruction is executed. flags: no flags are affected. format: (1) bytes cycles opcode (hex) addr mode dst src opc src | b | 1 dst 3 16/18 (2) 37 ra rb notes: 1. in the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. 2. execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 07h: btjrt skip,r1.1 if the working register r1 contains the value 07h (00000111b), the statement "btjrt skip,r1.1" tests bit one in the source register (r1). because it is a "1", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
s3c880a/f880a sam8 instruction set 6 - 25 bxor ? bit xor bxor dst,src.b bxor dst.b,src operation: dst(0) ? dst(0) xor src(b) or dst( b) ? dst(b) xor src(0) the specified bit of the source (or destination) is logically exclusive-ored with bit zero (lsb) of the destination (or source). the result bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 10 27 r0 rb opc src | b | 1 dst 3 10 27 rb r0 note : in the second byte of the 3-byte instruction format, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h (00000111b) and register 01h = 03h (00000011b): bxor r1,01h.1 ? r1 = 05h, register 01h = 03h bxor 01h.2,r1 ? register 01h = 07h, r1 = 07h in the first example, the destination working register r1 has the value 07h (00000111b) and the source register 01h has the value 03h (00000011b). the statement "bxor r1,01h.1" exclusive- ors bit one of the register 01h (source) with bit zero of r1 (destination). the result bit value is stored in bit zero of r1, changing its value from 07h to 05h. the value of the source register 01h is unaffected.
sam8 instruction set s3c880a/f880a 6 - 26 call ? call procedure call dst operation: sp ? sp ? 1 @sp ? pcl sp ? sp ?1 @sp ? pch pc ? dst the current contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 18 f6 da opc dst 2 18 f4 irr opc dst 2 20 d4 ia examples: given: r0 = 35h, r1 = 21h, pc = 1a47h, and sp = 0002h: call 3521h ? sp = 0000h (memory locations 0000h = 1ah, 0001h = 4ah, where 4ah is the address that follows the instruction.) call @rr0 ? sp = 0000h (0000h = 1ah, 0001h = 49h) call #40h ? sp = 0000h (0000h = 1ah, 0001h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0002h, the statement "call 3521h" pushes the current pc value onto the top of the stack. the stack pointer now points to the memory location 0000h. the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that 49h is stored in stack location 0001h (because the two-byte instruction format was used). the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. assuming that the contents of the program counter and stack pointer are the same as in the first example, if the program address 0040h contains 35h and the program address 0041h contains 21h, the statement "call #40h" produces the same result as in the second example.
s3c880a/f880a sam8 instruction set 6 - 27 ccf ? complement carry flag ccf operation: c ? not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero; if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 6 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction complements it in the flags register (0d5h), changing its value from logic zero to logic one.
sam8 instruction set s3c880a/f880a 6 - 28 clr ? clear clr dst operation: dst ? dst xor dst the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 6 b0 r b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h ? register 00h = 00h clr @01h ? register 01h = 02h, register 02h = 00h in register (r) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
s3c880a/f880a sam8 instruction set 6 - 29 com ? complement com dst operation: dst ? not dst the contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 6 60 r 61 ir examples: given: r1 = 07h and register 07h = 0f1h: com r1 ? r1 = 0f8h com @r1 ? r1 = 07h, register 07h = 0eh in the first example, the destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of the destination register 07h (11110001b), leaving the new value 0eh (00001110b).
sam8 instruction set s3c880a/f880a 6 - 30 cp ? compare cp dst,src operation: dst ? src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurre d; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 6 a2 r r a3 r lr opc src dst 3 10 a4 r r a5 r ir opc dst src 3 10 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 ? set the c and s flags the d estination working register r1 contains the value 02h and the source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, c and s are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, the destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in the working register r3.
s3c880a/f880a sam8 instruction set 6 - 31 cpije ? compare, increment, and jump on equal cpije dst,src,ra operation: if dst ? src = "0", pc ? pc + ra ir ? ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. otherwise, the instruction immediately following the cpije instruction is executed. in either case, the source pointer is incremented by one before the next instruction is executed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 16/18 c2 r ir note: execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 02h, r2 = 03h, and register 03h = 02h: cpije r1,@r2,skip ? r2 = 04h, pc jumps to skip location in this example, the working register r1 contains the value 02h, the w orking register r2 the value 03h, and the register 03h contains 02h. the statement "cpije r1,@r2,skip" compares the @r2 value 02h (00000010b) to 02h (00000010b). because the result of the comparison is equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source register (r2) is incremented by one, leaving a value of 04h. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
sam8 instruction set s3c880a/f880a 6 - 32 cpijne ? compare, increment, and jump on non-equal cpijne dst,src,ra operation: if dst ? src 1 "0", pc ? pc + ra ir ? ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the cpijne instruction is executed. in either case the source pointer is incremented by one before the next instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 16/18 d2 r ir note: execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 02h, r2 = 03h, and register 03h = 04h: cpijne r1,@r2,skip ? r2 = 04h, pc jumps to skip location the w orking register r1 contains the value 02h, the w orking register r2 (the source pointer) the value 03h, and the general register 03h contains the value 04h. the statement "cpijne r1,@r2,skip" subtracts 04h (00000100b) from 02h (00000010b). because the result of the comparison is non-equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source pointer register (r2) is also incremented by one, leaving a value of 04h. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
s3c880a/f880a sam8 instruction set 6 - 33 da ? decimal adjust da dst operation: dst ? da dst the destination operand is adjusted to form two 4-bit bcd digits after an addition or subtraction operation. for addition (add, adc) or subtraction (sub, sbc), the following table indicates the operation performed. (the operation is undefined if the destination operand was not the result of a valid addition or subtraction of bcd digits): instruction carry before da bits 4?7 value (hex) h flag before da bits 0?3 value (hex) number added to byte carry after da 0 0?9 0 0?9 00 0 0 0?8 0 a?f 06 0 0 0?9 1 0?3 06 0 add 0 a?f 0 0?9 60 1 adc 0 9?f 0 a?f 66 1 0 a?f 1 0?3 66 1 1 0?2 0 0?9 60 1 1 0?2 0 a?f 66 1 1 0?3 1 0?3 66 1 0 0?9 0 0?9 00 = ? 00 0 sub 0 0?8 1 6?f fa = ? 06 0 sbc 1 7?f 0 0?9 a0 = ? 60 1 1 6?f 1 6?f 9a = ? 66 1 flags: c: set if there was a carry from the most significant bit; cleared otherwise (see table). z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 6 40 r 41 ir
sam8 instruction set s3c880a/f880a 6 - 34 da ? decimal adjust da (continued) example: given: the w orking register r0 contains the value 15 (bcd), working register r1 contains 27 (bcd), and address 27h contains 46 (bcd): add r1,r0 ; c ? "0", h ? "0", bits 4?7 = 3, bits 0?3 = c, r1 ? 3ch da r1 ; r1 ? 3ch + 06 if an addition is performed using the bcd values 15 and 27, the result should be 42. the sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic: 0 0 0 1 0 1 0 1 15 + 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 = 3ch the da instruction adjusts this result so that the correct bcd representation is obtained: 0 0 1 1 1 1 0 0 + 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 = 42 assuming the same values given above, the statements sub 27h,r0 ; c ? "0", h "0", bits 4?7 = 3, bits 0?3 = 1 da @r1 ; @r1 ? 31?0 leave the value 31 (bcd) in the address 27h (@r1).
s3c880a/f880a sam8 instruction set 6 - 35 dec ? decrement dec dst operation: dst ? dst ? 1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 6 00 r 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 ? r1 = 02h dec @r1 ? register 03h = 0fh in the firs t example, if the working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
sam8 instruction set s3c880a/f880a 6 - 36 decw ? decrement word decw dst operation: dst ? dst ? 1 the contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 10 80 rr 81 ir examples: given: r0 = 12h, r1 = 34h, r2 = 30h, register 30h = 0fh, and register 31h = 21h: decw rr0 ? r0 = 12h, r1 = 33h decw @r2 ? register 30h = 0fh, register 31h = 20h in the first example, the destination register r0 contains the value 12h and the register r1 the value 34h. the statement "decw rr0" addresses r0 and the following operand r1 as a 16-bit word and decrements the value of r1 by one, leaving the value 33h. note: a system malfunction may occur if you use a zero flag (flags.6) result together with a decw instruction. to avoid this problem, we recommend that you use decw as shown in the following example: loop: decw rr0 ld r2,r1 or r2,r0 jr nz,loop
s3c880a/f880a sam8 instruction set 6 - 37 di ? disable interrupts di operation: sym (0) ? 0 bit zero of the system mode control register, sym.0, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 6 8f example: given: sym = 01h: di if the value of the sym regi ster is 01h, the statement "di" leaves the new value 00h in the register and clears sym.0 to "0", disabling interrupt processing.
sam8 instruction set s3c880a/f880a 6 - 38 div ? divide (unsigned) div dst,src operation: dst src dst (upper) ? remainder dst (lower) ? quotient the destination operand (16 bits) is divided by the source operand (8 bits). the quotient (8 bits) is stored in the lower half of the destination. the remainder (8 bits) is stored in the upper half of the destination. when the quotient is 3 2 8 , the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. both operands are treated as unsigned integers. flags: c: set if the v flag is set and the quotient is between 2 8 and 2 9 ?1; cleared otherwise. z: set if the divisor or quotient = "0"; cleared otherwise. s: set if the msb of quotient = "1"; cleared otherwise. v: set if the quotient is 3 2 8 or if the divisor = "0"; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 28/12 * 94 rr r 28/12 * 95 rr ir 28/12 * 96 rr im * execution takes 12 cycles if divide-by-zero is attempted; otherwise it takes 28 cycles. examples: given: r0 = 10h, r1 = 03h, r2 = 40h, register 40h = 80h: div rr0,r2 ? r0 = 03h, r1 = 40h div rr0,@r2 ? r0 = 03h, r1 = 20h div rr0,#20h ? r0 = 03h, r1 = 80h in the first example, the destination working register pair rr0 contains the values 10h (r0) and 03h (r1), and the register r2 contains the value 40h. the statement "div rr0,r2" divides the 16-bit rr0 value by the 8-bit value of the r2 (source) register. after the div instruction, r0 contains the value 03h and r1 contains 40h. the 8-bit remainder is stored in the upper half of the destination register rr0 (r0) and the quotient in the lower half (r1).
s3c880a/f880a sam8 instruction set 6 - 39 djnz ? decrement and jump if non-zero djnz r,dst operation: r ? r ? 1 if r 1 0, pc ? pc + dst the working register being used as a cou nter is decremented. if the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the pc. the range of the relative address is +127 to ?128, and the original value of the pc is taken to be the address of the instruction byte following the djnz statement. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst r | opc dst 2 12 (jump taken) ra ra 10 (no jump) r = 0 to f example: given: r1 = 02h and loop is the label of a relative address: djnz r1,loop djnz is typically used to control a "loop" of instructions. in many cases, a label is used as the destination operand instead of a numeric relative address value. in the example, the working register r1 contains the value 02h, and loop is the label for a relative address. the statement "djnz r1, loop" decrements the register r1 by one, leaving the value 01h. because the contents of r1 after the decrement are non-zero, the jump is taken to the relative address specified by the loop label. note: when pp = 11h or 10h and working register area is not in c0h?cfh, djnz instruction can not be used.
sam8 instruction set s3c880a/f880a 6 - 40 ei ? enable interrupts ei operation: sym (0) ? 1 an ei instruction sets bit zero of the system mode register, sym.0 to "1". this allows interrupts to be serviced as they occur (assuming they have highest priority). if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when you execute the ei instruction. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 6 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 01h, enabling all interrupts. (sym.0 is the enable bit for global interrupt processing.)
s3c880a/f880a sam8 instruction set 6 - 41 enter ? enter enter operation: sp ? sp ? 2 @sp ? ip ip ? pc pc ? @ip ip ? ip + 2 this instruction is useful when implementing threaded-code languages. the contents of the instruction pointer are pushed to the stack. the program counter (pc) value is then written to the instruction pointer. the program memory word that is pointed to by the instruction pointer is loaded into the pc, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 20 1f example: the diagram below shows one example of how to use an enter statement. 0050 1p 0022 sp 22 data address data 0040 pc 40 41 42 43 enter address h address l address h address data 1f 01 10 memory 0043 1p 0020 sp 20 21 22 iph ipl data address data 0110 pc 40 41 42 43 enter address h address l address h address data 1f 01 10 memory 00 50 stack stack 110 routine before after
sam8 instruction set s3c880a/f880a 6 - 42 exit ? exit exit operation: ip ? @sp sp ? sp + 2 pc ? @ip ip ? ip + 2 this instruction is useful when implementing threaded-code languages. the stack value is popped and loaded into the instruction pointer. the program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 22 2f example: the diagram below shows one example of how to use an exit statement. 0050 1p 0022 sp address data 0040 pc address data memory 0052 1p 0022 sp address data 0060 pc address data memory stack stack before after 22 data 20 21 22 iph ipl data 00 50 50 51 140 pcl old pch exit 60 00 2f 60 main
s3c880a/f880a sam8 instruction set 6 - 43 idle ? idle operation idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 3 6f ? ? example: the instruction idle stops the cpu clock but not the system clock.
sam8 instruction set s3c880a/f880a 6 - 44 inc ? increment inc dst operation: dst ? dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 6 re r r = 0 to f opc dst 2 6 20 r 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 ? r0 = 1ch inc 00h ? register 00h = 0dh inc @r0 ? r0 = 1bh, register 01h = 10h in the first example, if the destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the next example shows the effect an inc instruction has on the register 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of the register 1bh from 0fh to 10h.
s3c880a/f880a sam8 instruction set 6 - 45 incw ? increment word incw dst operation: dst ? dst + 1 the contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is neg ative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 10 a0 rr a1 ir examples: given: r0 = 1ah, r1 = 02h, register 02h = 0fh, and register 03h = 0ffh: incw rr0 ? r0 = 1ah, r1 = 03h incw @r1 ? register 02h = 10h, register 03h = 00h in the first example, the working register pair rr0 contains the value 1ah in the register r0 and 02h in the register r1. the statement "incw rr0" increments the 16-bit destination by one, leaving the value 03h in the register r1. in the second example, the statement "incw @r1" uses indirect register (ir) addressing mode to increment the contents of the general register 03h from 0ffh to 00h and the register 02h from 0fh to 10h. note: a system malfunction may occur if you use a zero (z) flag (flags.6) result together with an incw instruction. to avoid this problem, we recommend that you use incw as shown in the following example: loop: incw rr0 ld r2,r1 or r2,r0 jr nz,loop
sam8 instruction set s3c880a/f880a 6 - 46 iret ? interrupt return iret iret (normal) iret (fast) operation: flags ? @sp pc ? ip sp ? sp + 1 flags ? flags' pc ? @sp fis ? 0 sp ? sp + 2 sym(0) ? 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. a "normal iret" is executed only if the fast interrupt status bit (fis, bit one of the flags register, 0d5h) is cleared (= "0"). if a fast interrupt occurred, iret clears the fis bit that was set at the beginning of the service routine. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 16 bf iret (fast) bytes cycles opcode (hex) opc 1 6 bf example: in the figure below, the instruction pointer is initially loaded with 100h in the main program before interrupts are enabled. when an interrupt occurs, the program counter and the instruction pointer are swapped. this causes the pc to jump to the address 100h and the ip to keep the return address. the last instruction in the service routine normally is a jump to iret at the address ffh. this causes the instruction pointer to be loaded with 100h "again" and the program counter to jump back to the main program. now, the next interrupt can occur and the ip is still correct at 100h. iret interrupt service routine jp to ffh 0h ffh 100h ffffh n ote that in the fast interrupt example above, if the last instruction is not a jump to iret, you must pay attention to the order of the last two instructions. the iret cannot be immediately proceeded by clearing the interrupt status (as with a reset of the ipr register).
s3c880a/f880a sam8 instruction set 6 - 47 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc ? dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 10/12 (3) ccd da cc = 0 to f opc dst 2 10 30 irr notes : 1. the 3-byte format is used for a conditional jump and t he 2-byte format for an unconditional jump. 2. in the first byte of the 3 -byte instruction format (conditional jump), the condition code and the opcode are both four bits. 3. for a conditional jump, execution time is 12 cycles if the jump is taken or 10 cycles if it is not taken. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h: jp c,label_w ? label_w = 1000h, pc = 1000h jp @00h ? pc = 0120h the first example shows a conditional jp. assuming that the carry fla g is set to "1", the statement "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
sam8 instruction set s3c880a/f880a 6 - 48 jr ? jump relative jr cc,dst operation: if cc is true, pc ? pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the jr instruction is executed. (see the list of condition codes). the range of the relative address is +127 to ?128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (1) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 10/12 (2) ccb ra cc = 0 to f notes : 1. in the first byte of the two-byte instruction format, the condition code and the opcode are four bits each . 2. instruction execution time is 12 cycles if the jump is taken or 10 cycles if it is not taken. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x ? pc = 1ff7h if the carry flag is set (that is, if the condition code i s true), the statement "jr c,label_x" will pass control to the statement whose address is now in the pc. otherwise, the program instruction following the jr would be executed.
s3c880a/f880a sam8 instruction set 6 - 49 ld ? load ld dst,src operation: dst ? src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 6 rc r im 6 r8 r r src | opc dst 2 6 r9 r r r = 0 to f opc dst | src 2 6 c7 r lr 6 d7 ir r opc src dst 3 10 e4 r r 10 e5 r ir opc dst src 3 10 e6 r im 10 d6 ir im opc src dst 3 10 f5 ir r opc dst | src x 3 10 87 r x [r] opc src | dst x 3 10 97 x [r] r
sam8 instruction set s3c880a/f880a 6 - 50 ld ? l oad ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h ? r0 = 10h ld r0,01h ? r0 = 20h, register 01h = 20h ld 01h,r0 ? register 01h = 01h, r0 = 01h ld r1,@r0 ? r1 = 20h, r0 = 01h ld @r0,r1 ? r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h ? register 00h = 20h, register 01h = 20h ld 02h,@00h ? register 02h = 20h, register 00h = 01h ld 00h,#0ah ? register 00h = 0ah ld @00h,#10h ? register 00h = 01h, register 01h = 10h ld @00h,02h ? register 00h = 01h, register 01h = 02h, register 02h = 02h ld r0,#loop[r1] ? r 0 = 0ffh, r1 = 0ah ld #loop[r0],r1 ? register 31h = 0ah, r0 = 01h, r1 = 0ah
s3c880a/f880a sam8 instruction set 6 - 51 ldb ? load bit ldb dst,src.b ldb dst.b,src operation: dst(0) ? src(b) or dst(b) ? src(0) the specified bit of the source is loaded into bit zero (lsb) of the destination, or bit zero of the source is loaded into the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 10 47 r0 rb opc src | b | 1 dst 3 10 47 rb r0 note : in the second byte of the instruction format, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r0 = 06h and general register 00h = 05h: ldb r0,00h.2 ? r0 = 07h, register 00h = 05h ldb 00h.0,r0 ? r0 = 06h, register 00h = 04h in the first example, the destination working register r0 contains the value 06h and the source general register 00h the value 05h. the statement "ld r0,00h.2" loads the bit two value of the 00h register into bit zero of the r0 register, leaving the value 07h in the register r0. in the second example, 00h is the destination register. the statement "ld 00h.0,r0" loads bit zero of the register r0 to the specified bit (bit zero) of the destination register, leaving 04h in the general register 00h.
sam8 instruction set s3c880a/f880a 6 - 52 ldc/lde ? load memory ldc/lde dst,src operation: dst ? src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes 'irr' or 'rr' values an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 12 c3 r irr 2. opc src | dst 2 12 d3 irr r 3. opc dst | src xs 3 18 e7 r xs [rr] 4. opc src | dst xs 3 18 f7 xs [rr] r 5. opc dst | src xl l xl h 4 20 a7 r xl [rr] 6. opc src | dst xl l xl h 4 20 b7 xl [rr] r 7. opc dst | 0000 da l da h 4 20 a7 r da 8. opc src | 0000 da l da h 4 20 b7 da r 9. opc dst | 0001 da l da h 4 20 a7 r da 10. opc src | 0001 da l da h 4 20 b7 da r notes : 1. the source (src) or the working register pair [rr] for formats 5 and 6 cannot use the register pair 0?1. 2. for formats 3 and 4, the destination address 'xs [rr]' and the source address 'xs [rr]' are one byte each. 3. for formats 5 and 6, the destination address 'xl [rr] and the source address 'xl [rr]' are two bytes each. 4. the da and r source values for formats 7 and 8 are used to address program memory; the second set of values, u sed in formats 9 and 10, are used to address data memory.
s3c880a/f880a sam8 instruction set 6 - 53 ldc/lde ? l oad memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01 h, r3 = 04h; program memory locations 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 ? contents of program memory location 0104h ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 ? contents of external data memory location 0104h ; r0 = 2ah, r2 = 01h, r3 = 04h ldc (note) @rr2,r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change ldc r0,#01h[rr2] ; r0 ? contents of program memory location 0105h ; (01h + rr2), ; r0 = 6dh, r2 = 01h, r3 = 04h lde r0,#01h[rr2] ; r0 ? contents of external data memory location 0105h ; (01h + rr2), r0 = 7dh, r2 = 01h, r3 = 04h ldc (note) #01h[rr2],r0 ; 11h (contents of r0) is loaded into program memory location ; 0105h (01h + 0104h) lde #01h[rr2],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0105h (01h + 0104h) ldc r0,#1000h[rr2] ; r0 ? contents of program memory location 1104h ; (1000h + 0104h), r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 ? contents of external data memory location 1104h ; (1000h + 0104h), r0 = 98h, r2 = 01h, r3 = 04h ldc r0,1104h ; r0 ? contents of program memory location 1104h, r0 = 88h lde r0,1104h ; r0 ? contents of external data memory location 1104h, ; r0 = 98h ldc (note) 1105h,r0 ; 11h (contents of r0) is loaded into program memory location ; 1105h, (1105h) ? 11h lde 1105h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h, (1105h) ? 11h note: these instructions are not supported by masked rom type devices.
sam8 instruction set s3c880a/f880a 6 - 54 ldcd/lded ? load memory and decrement ldcd/lded dst,src operation: dst ? src rr ? rr ? 1 these instructions are used for user s tacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd refers to program memory and lded refer s to external data memory. the assembler makes 'irr' an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 16 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is decremented by one ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 ? rr6 ? 1) lded r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 a nd rr6 is decremented by one (rr6 ? rr6 ? 1) ; r8 = 0ddh, r6 = 10h, r7 = 32h
s3c880a/f880a sam8 instruction set 6 - 55 ldci/ldei ? load memory and increment ldci/ldei dst,src operation: dst ? src rr ? rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes 'irr' even number for program memory and odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 16 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0ddh, r6 = 10h, r7 = 34h
sam8 instruction set s3c880a/f880a 6 - 56 ldcpd/ldepd ? load memory with pre-decrement ldcpd/ ldepd dst,src operation: rr ? rr ? 1 dst ? src the se instructions are used for block transfers of data from program or data memory from the register file. the address of the memory location is specified by a working register pair and is first decremented. the contents of the source location are then loaded into the destination location. the contents of the source are unaffected. ldcpd refers to program memory and ldepd refers to external data memory. the assembler makes 'irr' an even number for program memory and an odd number for external data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 16 f2 irr r examples: given: r0 = 77h, r6 = 30h, and r7 = 00h: ldcpd @rr6,r0 ; (rr6 ? rr6 ? 1) ; 77h (contents of r0) is loaded into program memory location ; 2fffh (3000h ? 1h) ; r0 = 77h, r6 = 2fh, r7 = 0ffh ldepd @rr6,r0 ; (rr6 ? rr6 ? 1) ; 77h (contents of r0) is loaded into external data memory ; location 2fffh (3000h ? 1h) ; r0 = 77h, r6 = 2fh, r7 = 0 ffh
s3c880a/f880a sam8 instruction set 6 - 57 ldcpi/ldepi ? load memory with pre-increment ldcpi/ ldepi dst,src operation: rr ? rr + 1 dst ? src these instructions are used for block transfers of data from program or data memory from the register file. the address of the memory location is specified by a working register pair and is first incremented. the contents of the source location are loaded into the destination location. the contents of the source are unaffected. ldcpi refers to program memory and ldepi re fers to external data memory. the assembler makes 'irr' an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 16 f3 irr r examples: given: r0 = 7fh, r6 = 21h, and r7 = 0ffh: ldcpi @rr6,r0 ; (rr6 ? rr6 + 1) ; 7fh (contents of r0) is loaded into program memory ; location 2200h (21ffh + 1h) ; r0 = 7fh, r6 = 22h, r7 = 00h ldepi @rr6,r0 ; (rr6 ? rr6 + 1) ; 7fh (contents of r0) is loaded into external data memory ; location 2200h (21ffh + 1h) ; r0 = 7fh, r6 = 22h, r7 = 00h
sam8 instruction set s3c880a/f880a 6 - 58 ldw ? load word ldw dst,src operation: dst ? src the contents of the source (a word) are loaded into the destination. the contents of the source are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 10 c4 rr rr 10 c5 rr ir opc dst src 4 12 c6 rr iml examples: given: r4 = 06h, r5 = 1ch, r6 = 05h, r7 = 02h, register 00h = 1ah, register 01h = 02h, register 02h = 03h, and register 03h = 0fh: ldw rr6,rr4 ? r6 = 06h, r7 = 1ch, r4 = 06h, r5 = 1ch ldw 00h,02h ? register 00h = 03h, register 01h = 0fh, register 02h = 03h, register 03h = 0fh ldw rr2,@r7 ? r2 = 03h, r3 = 0fh, ldw 04h,@01h ? register 04h = 03h, register 05h = 0fh ldw rr6,#1234h ? r6 = 12h, r7 = 34h ldw 02h,#0fedh ? register 02h = 0fh, register 03h = 0edh in the second example, please note that the statement "ldw 00h,02h" loads the contents of the source word 02h, 03h into the destination word 00h, 01h. this leaves the value 03h in the general register 00h and the value 0fh in the register 01h. o ther examples show how to use the ldw instruction with various addressing modes and formats.
s3c880a/f880a sam8 instruction set 6 - 59 mult ? multiply (unsigned) mult dst,src operation: dst ? dst src the 8-bit destination operand ( the even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. both operands are treated as unsigned integers. flags: c: set if the result is > 255; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if msb of the result is a "1"; cleared otherwise. v: cleared. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 24 84 rr r 24 85 rr ir 24 86 rr im examples: given: register 00h = 20h, register 01h = 03h, register 02h = 09h, register 03h = 06h: mult 00h, 02h ? register 00h = 01h, register 01h = 20h, register 02h = 09h mult 00h, @01h ? register 00h = 00h, register 01h = 0c0h mult 00h, #30h ? register 00h = 06h, register 01h = 00h in the first example, the statement "mult 00h,02h" multiplies the 8-bit destination operand (in the register 00h of the register pair 00h, 01h) by the source register 02h operand (09h). the 16 -bit product, 0120h, is stored in the register pair 00h, 01h.
sam8 instruction set s3c880a/f880a 6 - 60 next ? next next operation: pc ? @ip ip ? ip + 2 the next instruction is useful when implementing threaded-code languages. the program memory word that is pointed to by the instruction pointer is loaded into the program counter. the instruction pointer is then incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 0f example: the following diagram shows one example of how to use the next instruction. data 01 10 before after 0045 1p address data 0130 pc 43 44 45 address h address l address h address data memory 130 routine 0043 1p address data 0120 pc 43 44 45 address h address l address h address data memory 120 next
s3c880a/f880a sam8 instruction set 6 - 61 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typically, one or more nops are executed in sequence in order to effect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 6 ff example: when the instruction nop is encountered in a program, no operation occurs. instead, there happen s a delay in instruction execution.
sam8 instruction set s3c880a/f880a 6 - 62 or ? logical or or dst,src operation: dst ? dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 6 42 r r 6 43 r lr opc src dst 3 10 44 r r 10 45 r ir opc dst src 3 10 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah: or r0,r1 ? r0 = 3fh, r1 = 2ah or r0,@r2 ? r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h ? register 00h = 3fh, register 01h = 37h or 01h,@00h ? register 00h = 08h, register 01h = 0bfh or 00h,#02h ? register 00h = 0ah in the first example, if the working register r0 contains the value 15h and the register r1 the value 2ah, the statement "or r0,r1" logical-ors the r0 and r1 register contents and stores the result (3fh) in the destination register r0. o ther examples show the use of the logical or instruction with the various addressing modes and formats.
s3c880a/f880a sam8 instruction set 6 - 63 pop ? pop from stack pop dst operation: dst ? @sp sp ? sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 10 50 r 10 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sph (0d8h) = 00h, spl (0d9h) = 0fbh, and stack register 0fbh = 55h: pop 00h ? register 00h = 55h, sp = 00fch pop @00h ? register 00h = 01h, register 01h = 55h, sp = 00fch in the first example, the general register 00h contains the value 01h. the statement "pop 00h" loads the contents of the location 00fbh (55h) into the destination register 00h and then increments the stack pointer by one. the r egister 00h then contains the value 55h and the sp points to the location 00fch.
sam8 instruction set s3c880a/f880a 6 - 64 popud ? pop user stack (decrementing) popud dst,src operation: dst ? src ir ? ir ? 1 this instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then decremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 10 92 r ir example: given: register 00h = 42h (user stack pointer register), register 42h = 6fh, and register 02h = 70h: popud 02h,@00h ? register 00h = 41h, register 02h = 6fh, register 42h = 6fh if the general register 00h contains the value 42h and the register 42h the value 6fh, the statement "popud 02h,@00h" loads the contents of the register 42h into the destination register 02h. the user stack pointer is then decremented by one, leaving the value 41h.
s3c880a/f880a sam8 instruction set 6 - 65 popui ? pop user stack (incrementing) popui dst,src operation: dst ? src ir ? ir + 1 the popui instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then incremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 10 93 r ir example: given: register 00h = 01h and register 01h = 70h: popui 02h,@00h ? register 00h = 02h, register 01h = 70h, register 02h = 70h if the general register 00h contains the value 01h and the register 01h the value 70h, the statement "popui 02h,@00h" loads the value 70h into the destination general register 02h. the user stack pointer (register 00h) is then incremented by one, changing its value from 01h to 02h.
sam8 instruction set s3c880a/f880a 6 - 66 push ? push t o stack push src operation: sp ? sp ? 1 @sp ? src a push instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 10 (internal clock) 70 r 12 (external clock) 12 (internal clock) 14 (external clock) 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sph = 00h, and spl = 00h: push 40h ? register 40h = 4fh, stack register 0ffh = 4fh, sph = 0ffh, spl = 0ffh push @40h ? register 40h = 4fh, register 4fh = 0aah, stack register 0ffh = 0aah, sph = 0ffh, spl = 0ffh in the first example, if the stack pointer contains the value 0000h, and the general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0000 to 0ffffh. it then loads the contents of the register 40h into the location 0ffffh and adds this new value to the top of the stack.
s3c880a/f880a sam8 instruction set 6 - 67 pushud ? push user stack (decrementing) pushud dst,src operation: ir ? ir ? 1 dst ? src this instruction is used to address user-defined stacks in the register file. pushud decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 10 82 ir r example: given: register 00h = 03h, register 01h = 05h, and register 02h = 1ah: pushud @00h,01h ? register 00h = 02h, register 01h = 05h, register 02h = 05h if the user stack pointer (register 00h, for example) contains the value 03h, the statement "pushud @00h,01h" decrements the user stack pointer by one, leaving the value 02h. the 01h register value, 05h, is then loaded into the register addressed by the decremented user stack pointer.
sam8 instruction set s3c880a/f880a 6 - 68 pushui ? push user stack (incrementing) pushui dst,src operation: ir ? ir + 1 dst ? src this instruction is used for user-defined stacks in the register file. pushui increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 10 83 ir r example: given: register 00h = 03h, register 01h = 05h, and register 04h = 2ah: pushui @00h,01h ? register 00h = 04h, register 01h = 05h, register 04h = 05h if the user stack pointer (register 00h, for example) contains the value 03h, the statement "pushui @00h,01h" increments the user stack pointer by one, leaving the value 04h. the 01h register value, 05h, is then loaded into the location addressed by the incremented user stack pointer.
s3c880a/f880a sam8 instruction set 6 - 69 rcf ? reset carry flag rcf rcf operation: c ? 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 6 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
sam8 instruction set s3c880a/f880a 6 - 70 ret ? return ret operation: pc ? @sp sp ? sp + 2 the ret instru ction is normally used to return to the previously execut ed procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement that is executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 af example: given: sp = 00fch, (sp) = 101ah, and pc = 1234: ret ? pc = 101ah, sp = 00feh th e statement "ret" pops the contents of the stack pointer location 00fch (10h) into the high byte of the program counter. the stack pointer then pops the value in the location 00feh (1ah) into the pc's low byte and the instruction at the location 101ah is executed. the stack pointer now points to the memory location 00feh.
s3c880a/f880a sam8 instruction set 6 - 71 rl ? rotate left rl dst operation: c ? dst (7) dst (0) ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value of bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag. 7 0 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 6 90 r 6 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h ? register 00h = 55h, c = "1" rl @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if the general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry and overflow flags.
sam8 instruction set s3c880a/f880a 6 - 72 rlc ? rotate left through carry rlc dst operation: dst (0) ? c c ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the contents of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c); the initial value of the carry flag replaces bit zero. 7 0 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arit hmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 6 10 r 6 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h ? register 00h = 54h, c = "1" rlc @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if the general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of the register 00h, leaving the value 55h (01010101b). the msb of the register 00h resets the carry flag to "1" , setting the overflow flag.
s3c880a/f880a sam8 instruction set 6 - 73 rr ? rotate right rr dst operation: c ? dst (0) dst (7) ? dst (0) dst (n) ? dst (n + 1), n = 0?6 the contents of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). 7 0 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 6 e0 r 6 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h ? register 00h = 98h, c = "1" rr @01h ? register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if the general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and overflow flag are also set to "1".
sam8 instruction set s3c880a/f880a 6 - 74 rrc ? rotate right through carry rrc dst operation: dst (7) ? c c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag; the initial value of the carry flag replaces bit 7 (msb). 7 0 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 6 c0 r 6 c1 ir examples: given: register 00h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h ? register 00h = 2ah, c = "1" rrc @01h ? register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if the general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c flag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in the destination register 00h. the sign flag and the overflow flag are both cleared to "0".
s3c880a/f880a sam8 instruction set 6 - 75 sb0 ? select bank 0 sb0 operation: bank ? 0 the sb0 instruction clears the bank address flag in the flags register (flags.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 6 4f example: the statement sb0 clears flags.0 to "0", selecting bank 0 register addressing.
sam8 instruction set s3c880a/f880a 6 - 76 sb1 ? select bank 1 sb1 operation: bank ? 1 the sb1 instruction sets the bank address flag in the flags register (flags.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (bank 1 is not implemented in some ks88-series microcontrollers.) flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 6 5f example: the statement sb1 sets flags.0 to "1", selecting bank 1 register addressing, if implemented.
s3c880a/f880a sam8 instruction set 6 - 77 sbc ? subtract w ith carry sbc dst,src operation: dst ? dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 6 32 r r 6 33 r lr opc src dst 3 10 34 r r 10 35 r ir opc dst src 3 10 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: sbc r1,r2 ? r1 = 0ch, r2 = 03h sbc r1,@r2 ? r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h ? register 01h = 1ch, register 02h = 03h sbc 01h ,@02h ? register 01h = 15h,register 02h = 03h, register 03h = 0ah sbc 01h,#8ah ? register 01h = 95h; c, s, and v = "1" in the first example, if the working register r1 contains the value 10h and the register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in the register r1.
sam8 instruction set s3c880a/f880a 6 - 78 scf ? set carry flag scf operation: c ? 1 the carry flag (c) is set to logic one, rega rdless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 6 df example: the statement scf sets the carry flag to logic one.
s3c880a/f880a sam8 instruction set 6 - 79 sra ? shift right arithmetic sra dst operation: dst (7) ? dst (7) c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is performed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into the bit position 6. 7 0 c 6 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 6 d0 r 6 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h ? register 00h = 0cdh, c = "0" sra @02h ? register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if the general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in the register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in the destination register 00h.
sam8 instruction set s3c880a/f880a 6 - 80 srp/srp0/srp1 ? set register pointer srp src srp0 src srp1 src operation: if src (1) = 1 and src (0) = 0 then: rp0 (3 ?7) ? src (3 ?7) if src (1) = 0 and src (0) = 1 then: rp1 (3 ?7) ? src (3 ?7) if src (1) = 0 and src (0) = 0 then: rp0 (4 ?7) ? src (4 ?7), rp0 (3) ? 0 rp1 (4 ?7) ? src (4 ?7), rp1 (3) ? 1 the source data bits one and zero (lsb) determine whether to write one or both of the register pointers, rp0 and rp1. bits 3?7 of the selected register pointer are written unless both register pointers are selected. rp0.3 is then cleared to logic zero and rp1.3 is set to logic one. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode src opc src 2 6 31 im examples: the statement srp #40h sets the register pointer 0 (rp0) at location 0d6h to 40h and the register pointer 1 (rp1) at location 0d7h to 48h. the statement "srp0 #50h" sets rp0 to 50h, and the statement "srp1 #68h" sets rp1 to 68h.
s3c880a/f880a sam8 instruction set 6 - 81 stop ? stop operation stop operation: the stop instruction stops both the cpu clock and the system clock causing the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released only by an external reset operation. for the reset operation, the nreset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 3 7f ? ? example: the statement stop halts all microcontroller operations.
sam8 instruction set s3c880a/f880a 6 - 82 sub ? subtract sub dst,src operation: dst ? dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise , indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 6 22 r r 6 23 r lr opc src dst 3 10 24 r r 10 25 r ir opc dst src 3 10 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 ? r1 = 0fh, r2 = 03h sub r1,@r2 ? r1 = 08h, r2 = 03h sub 01h,02h ? register 01h = 1eh, register 02h = 03h sub 01h,@02h ? register 01h = 17h, register 02h = 03h sub 01h,#90h ? register 01h = 91h; c, s, and v = "1" sub 01h,#65h ? register 01h = 0bch; c and s = "1", v = "0" in the first example, if the working register r1 contains the value 12h and the register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) , stor ing the result (0fh) in the destination register r1.
s3c880a/f880a sam8 instruction set 6 - 83 swap ? swap nibbles swap dst operation: dst (0 ? 3) ? dst (4 ? 7) the contents of the lower four bits and the upper four bits of the destination operand are swapped. 7 0 4 3 flags: c: undefined. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 f0 r 8 f1 ir examples: given: register 00h = 3eh, register 02h = 03h, and register 03h = 0a4h: swap 00h ? register 00h = 0e3h swap @02h ? register 02h = 03h, register 03h = 4ah in the first example, if the general register 00h contains the value 3eh (00111110b), the statement "swap 00h" swaps the lower and the upper four bits (nibbles) in the 00h register, leaving the value 0e3h (11100011b).
sam8 instruction set s3c880a/f880a 6 - 84 tcm ? test complement u nder mask tcm dst,src operation: (not dst) and src this instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 6 62 r r 6 63 r lr opc src dst 3 10 64 r r 10 65 r ir opc dst src 3 10 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "1" tcm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tcm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 ? register 00h = 2bh, z = "0" in the first example, if the working register r0 contains the value 0c7h (11000111b) and the register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
s3c880a/f880a sam8 instruction set 6 - 85 tm ? test u nder mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero val ue. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 6 72 r r 6 73 r lr opc src dst 3 10 74 r r 10 75 r ir opc dst src 3 10 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 ? r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h ? register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h ? register 00h = 2bh, reg ister 01h = 02h, register 02h = 23h, z = "0" tm 00h,#54h ? register 00h = 2bh, z = "1" in the first example, if the working register r0 contains the value 0c7h (11000111b) and the register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
sam8 instruction set s3c880a/f880a 6 - 86 wfi ? wait f or interrupt wfi operation: the cpu is effectively halted until an interrupt occurs, except in the case that dma transfers can still take place during this wait state. the wfi status can be released by an internal interrupt, including a fast interrupt . flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 6n 3f ( n = 1, 2, 3, ? ) example: the following sample program structure shows the sequence of operations that follow a "wfi" statement: ei wfi (next instruction) main program . . . . . . interrupt occurs interrupt service routine . . . clear interrupt flag iret service routine completed (enable global interrupt) (wait for interrupt)
s3c880a/f880a sam8 instruction set 6 - 87 xor ? logical exclusive or xor dst,src operation: dst ? dst xor src the source operand is logically exclusive-ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaf fected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 6 b2 r r 6 b3 r lr opc src dst 3 10 b4 r r 10 b5 r ir opc dst src 3 10 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0,r1 ? r0 = 0c5h, r1 = 02h xor r0,@r1 ? r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h ? register 00h = 29h, register 01h = 0 2h xor 00h,@01h ? register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h,#54h ? register 00h = 7fh in the first example, if the working register r0 contains the value 0c7h and the register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive-ors the r1 value with the r0 value , stor ing the result (0c5h) in the destination register r0.
sam8 instruction set s3c880a/f880a 6 - 88 notes
s3c880a/f880a clock circuits 7- 1 7 clock circuits overview the clock frequency generated by an external crystal or ceramic resonator may range from 0.5 mhz to 8 mhz. the maximum cpu clock frequency is 8 mhz. the x in and x out pins connect the external oscillation source to the on- chip clock circuit. a separate external l-c resonator circuit generates a clock pulse for the on-screen display (osd) block. system clock circuit the system clock circuit has the following components: ? external crystal or ceramic oscillation source ? oscillator stop and wake-up functions ? programmable frequency divider for the cpu clock (f osc divided by 1, 2, 8, or 16) ? clock circuit control register, clkcon s3c880a/f880a x in x out c1 c2 note: in x in, x out pin, 10 pf load capacitor is built-in. figure 7-1. main oscillator circuit (external crystal or ceramic resonator)
clock circuits s3c880a/f880a 7- 2 clock status during power-down modes the two power-down modes, stop mode and idle mode, affect system clock oscillation as follows: ? in stop mode, the main oscillator is halted. stop mode is released, and the oscillator started, by a reset operation or by an external interrupt (with rc-delay noise filter). ? in idle mode, the internal clock signal is gated off to the cpu and to all p eripherals except for the osd block, timer a counter, pwm, and capture (capa), which are inactive. idle mode is released by a reset or by all interrupt. main osc noise filter oscillator wake-up oscillator stop clkcon.7 int pin (1) stop instruction notes: 1. an external interrupt (with rc-delay noise filter) can be used to release stop mode and "wake up" the main oscillator. this interrupt type includes int0-int3 and capa input. 2. for S3F880A, the clkcon signature code (clkcon.0-clkcon.2) should not be '101b' (because no subsystem clock is implemented) clkcon.3, .4 1/2 1/8 1/16 m u x clkcon.0-.2 3-bit signature code (2) m u x cpu clock clkcon.5, .6 figure 7-2. system clock circuit diagram
s3c880a/f880a clock circuits 7- 3 system clock control register (clkcon) the system clock control register, clkcon, is located in set 1 at address d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable ? main oscil lator stop control ? oscillator frequency divide-by value: non-divided, 2, 8, or 16 ? system clock signal selection the clkcon register controls whether or not an external interrupt can be used to trigger a power-down mode release. (this is called the "irq wake-up" function.) the irq wake-up enable bit is clkcon.7. after a reset, the external interrupt oscillator wake-up bit is set to "1", the main oscillator is activated, and the f osc /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f osc , f osc /2, or f osc /8. for the s3c880a/f880a, the clkcon.0?clkcon.2 system clock signature code should be any value other than '101b'. (this setting is invalid because a subsystem clock is not implemented.) the reset value for the clock signature code is '000b'. system clock control register (clkcon) d4h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb divide-by selection bits for cpu clock frequency: 00 = f osc /16 01 = f osc /8 10 = f osc /2 11 = f osc /(non-divided) system clock selection bits: (note) 101b = invalid selection other value = normal operating mode main oscillator stop control bits: (note) 00 = no effect 01 = no effect 10 = stop main oscillator 11 = no effect oscillator irq wake-up enable bit: 0 = enable irq for main system oscillator wake-up in power-down mode 1 = disable irq for main system oscillator wake-up in power-down mode note: not used in s3c880a. these setting is valid in subsystem clock operation. s3c880a is not implemented subsystem operation function. figure 7-3. system clock control register (clkcon)
clock circuits s3c880a/f880a 7- 4 l-c oscillator circuit the l-c oscillator circuit has the following components: ? extern al l-c oscillator with a 5-8 mhz frequency range ? oscillator clock divider value (chacon.4 and chacon.5) ? osc in and osc out pins ? on/off control bit (dspcon.0) red-green-blue (rgb) color outputs, as well as display rates and positions, are determined by the l-c clock signal. this signal is scaled by the dot and column counter. the clock signal equals to the osd oscillator clock divided by the clock divider value. the clock divider value is determined by the horizontal character size settings in the chacon register. the rate at which each new display line is generated is determined strictly by the h-sync input. the rate at which each new frame (screen) is generated is determined by the v-sync input. note: for stable on screen display operation, the cpu clock frequency should faster than l-c (osd) clock. s3c880a/f880a osc in osd out c1 = 20 pf c2 = 20 pf l figure 7-4. l-c oscillator circuit for osd
s3c880a/f880a clock circuits 7- 5 l-c oscillator operating condition to operate the lc oscillator, the following conditions must be satisfied. ? lc oscillator operation m ust be enabled by setting dspcon.0 to ?1?. ? v-sync signal and h-sync signal must be input. ? lc oscillator must be operated except at the range of h-sync blanking and v-sync blanking. v-sync signal h-sync signal l-c osc on l-c osc off v-sync blanking range h-sync blanking range relation between l-c oscillator and cpu clock for normal on screen display, l-c oscillator less than cpu clock + 10 % is better. for 8 mhz cpu clock, an active l-c oscillator clock range is lower than 9mhz.
clock circuits s3c880a/f880a 7- 6 notes
s3c880a/f880a n reset and power-down 8 - 1 8 n reset and power-down system n reset overview during a power-on reset, the voltage at v dd is high level and the nreset pin is forced to low level. the nreset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this brings the s3c880a/f880a into a normal operating status. the nreset pin must be held to low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal cpu clock oscillation to stabilize. the minimum time required for oscillation stabilization for a reset is 1 millisecond. when a reset occurs during the normal operation (that is, when v dd and nreset are high level), the nreset pin is forced low and the reset operation starts. all system and peripheral control registers are set to their default hardware reset values (see table 8 - 1). in summary, the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports p0.0?p0.5, p1.6?p1.7 and p2 are set to input mode, and p0.6?p0.7, p1.0?p1.5 and p3, these ports set to n-channel open-drain output mode. ? peripheral control and data reg isters are disabled and reset to their initial control values. ? the program counter is loaded with the rom's reset address, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the instruction stored in the rom location 0100h (and 0101h) is fetched and executed. note you can program the duration of the oscillation stabilization interval by making the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, you if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010b' to the upper nibble of btcon.
n reset and power-down s3c880a/f880a 8 - 2 hardware reset values tables 8 - 1 through 8 -3 list the reset values for cpu and system registers, peripheral control registers, and peripheral data registers after a reset operation. the following notation is used to represent reset values: ? a "1" or a "0" shows the reset bit value as logic one or log ic zero, respectively. ? an 'x' means that the bit value is undefined after a reset. ? a dash (' ?') means that the bit is either not used or not mapped. table 8 - 1. set 1 register values a fter a reset register name mnemonic address bit values after a reset dec hex 7 6 5 4 3 2 1 0 timer 0 counter t0cnt 208 d0h 0 0 0 0 0 0 0 0 timer 0 data register t0data 209 d1h 1 1 1 1 1 1 1 1 timer 0 control register t0con 210 d2h 0 0 0 0 0 0 0 0 basic timer control register btcon 211 d3h 0 0 0 0 0 0 0 0 clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h x x x x x x 0 0 register pointer 0 rp0 214 d6h 1 1 0 0 0 ? ? ? register pointer 1 rp1 215 d7h 1 1 0 0 1 ? ? ? stack pointer (high byte) sph 216 d8h x x x x x x x x stack pointer (low byte) spl 217 d9h x x x x x x x x instruction pointer (high byte) iph 218 dah x x x x x x x x instruction pointer (low byte) ipl 219 dbh x x x x x x x x interrupt request register irq 220 dch 0 0 ? 0 0 0 0 0 interrupt mask register imr 221 ddh x x ? x x x x x system mode register sym 222 deh 0 ? 0 x x x 0 0 register page pointer pp 223 dfh 0 0 0 0 0 0 0 0 note: although it is not used for the s3c880a/f880a, bit 5 of the sym register should always be "0". if this bit is accidentally written to "1" by software, a system malfunction may occur.
s3c880a/f880a n reset and power-down 8 - 3 table 8 - 2. set 1, bank 0 register values a fter a reset register name mnemonic address bit values after a reset dec hex 7 6 5 4 3 2 1 0 port 0 data register p0 224 e0h 0 0 0 0 0 0 0 0 port 1 data register p1 225 e1h 0 0 0 0 0 0 0 0 port 2 data register p2 226 e2h 0 0 0 0 0 0 0 0 port 3 data register p3 227 e3h ? ? ? ? ? ? 0 0 port 0 control register (high byte) p0conh 228 e4h 1 1 1 1 0 0 0 0 port 0 control register (low byte) p0conl 229 e5h 0 0 0 0 0 0 0 0 port 1 control register (high byte) p1conh 230 e6h 0 0 0 0 1 1 1 1 port 1 control register (low byte) p1conl 231 e7h 1 1 1 1 1 1 1 1 port 2 control register (high byte) p2conh 232 e8h 0 0 0 0 0 0 0 0 port 2 control register (low byte) p2conl 233 e9h 0 0 0 0 0 0 0 0 location eah in set 1, bank 0, are not mapped. port 3 control register (low byte) p3conl 235 ebh ? ? ? ? 1 1 1 1 locations ech?efh in set 1, bank 0, are not mapped. timer a data register tadata 240 f0h 0 0 0 0 0 0 0 0 location f1h in set 1, bank 0, are not mapped. timer a control register tacon 242 f2h 0 0 0 0 0 0 0 ? stop control register stcon 238 f3h 0 0 0 0 0 0 0 0 pwm0 data register (main byte) pwm0 244 f4h 1 1 1 1 1 1 1 1 pwm0 data register (extension byte) pwm0ex 245 f5h 0 0 0 0 0 0 ? ? pwm1 data register (main byte) pwm1 246 f6h 1 1 1 1 1 1 1 1 pwm1 data register (extension byte) pwm1ex 247 f7h 0 0 0 0 0 0 ? ? pwm control register pwmcon 248 f8h 0 0 0 0 0 ? 0 0 capture a data register capa 249 f9h 0 0 0 0 0 0 0 0 a/d converter control register adcon 250 fah ? ? 0 0 x 0 0 0 a/d conversion data register addata 251 fbh x x x x x x x x location fch in set 1, bank 0, are not mapped. basic timer counter btcnt 253 fdh 0 0 0 0 0 0 0 0 external memory timing register emt 254 feh 0 0 0 0 0 0 0 ? interrupt priority register ipr 255 ffh x x ? x x x x x
n reset and power-down s3c880a/f880a 8 - 4 table 8 - 2. set 1, bank 1 register values a fter a reset register name mnemonic address bit values after a reset dec hex 7 6 5 4 3 2 1 0 osd fringe/border control register 1 osdfrg1 224 e0h 0 0 0 0 0 0 0 0 osd fringe/border control register 2 osdfrg2 225 e1h 0 0 0 0 0 0 0 0 osd smooth control register 1 osdsmh1 226 e2h 0 0 0 0 0 0 0 0 osd smooth control register 2 osdsmh2 227 e3h ? ? ? ? 0 0 0 0 osd space color control register osdcol 236 e4h ? ? ? ? 0 0 0 0 osd field control register osdfld 237 e5h ? ? x 0 0 1 1 0 osd palette color mode r 1 osdpltr1 230 e6h 0 0 0 0 0 0 0 0 osd palette color mode r 2 osdpltr2 231 e7h 1 1 1 1 1 1 1 1 osd palette color mode g 1 osdpltg1 232 e8h 1 1 1 1 0 0 0 0 osd palette color mode g 2 osdpltg2 233 e9h 1 1 1 1 0 0 0 0 osd palette color mode b 1 osdpltb1 234 eah 1 1 0 0 1 1 0 0 osd palette color mode b 2 osdpltb2 235 ebh 1 1 0 0 1 1 0 0 locations ech?efh in set 1, bank 1, are not mapped. osd character size control register chacon 240 f0h 0 0 0 0 0 0 0 0 osd fade control register fadecon 241 f1h 0 0 0 0 0 0 0 0 osd row position control register rowcon 242 f2h 0 0 0 0 0 0 0 0 osd column position control register clmcon 243 f3h 0 0 0 0 0 0 0 0 osd background color control register colcon 244 f4h 0 0 0 0 0 0 0 0 on-screen display control register dspcon 245 f5h 0 0 0 0 0 0 0 0 halftone signal control register htcon 246 f6h 0 0 0 0 0 0 0 0 v-sync blank control register vsbcon 252 f7h ? ? ? 0 1 0 0 1 pwm2 data register pwm2 248 f8h x x x x x x x x pwm3 data register pwm3 249 f9h x x x x x x x x pwm4 data register pwm4 250 fah x x x x x x x x pwm5 data register pwm5 251 fbh x x x x x x x x osd color buffer colbuf 247 fch ? ? ? x x x x x locations fdh?ffh in set 1, bank 1, are not mapped. table 8 -3 . page 1 video ram register values a fter a reset register name address bit values after a reset 7 6 5 4 3 2 1 0 osd video ram 00h?fbh x x x x x x x x
s3c880a/f880a n reset and power-down 8 - 5 power-down modes stop mode stop mode is invoked by the instruction s top (opcode 7fh) however stop available state must be set by value "10100101b" in "stcon" register before stop instruction is invoked. if stop instruction (opcode 7fh) is executed in stop not available state (stcon = other value except "10100101b") cpu go to reset address. after stop instruction is executed the state return to stop not available state. in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than maximum 10 a. all system functions stop when the clock "freezes," but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a nreset signal or by an external interrupt. using nreset to release stop mode stop mode is released when the nreset signal goes inactive (high level) from active (low level) state . all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. a reset operation automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. after the programmed oscillation stabilization interval has elapsed, the cpu starts the system initialization routine by fetching the address stored in the rom location 0100h. using an external interrupt to release stop mode two kinds of external interrupts with an rc-delay noise filter circuit can be used to release stop mode. one external interrupts in the s3c880a/f880a interrupt structure that meet this requirement are int0?int 3 (p 1.0 ?p 1.3) and the other one is v-sync input . which interrupt you can use to release stop mode in a given situation depends on the microcontroller's current internal operating mode. note that when stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. when you use an interrupt to release stop mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. i f you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. the external interrupt is serviced when a stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed.
n reset and power-down s3c880a/f880a 8 - 6 idle mode idle mode is invoked by the instruction idle (opcode 6fh). in idle mode, the cpu operations are halted while select ed peripherals remain active. during idle mode, the internal clock signal is gated off to the cpu and all peripherals except the osd block timer a counter, pwm and capture (capa) . port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. if interrupts are masked, a reset is the only way to release idle mode. 2. activate any enabled interrupt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt (iret) occurs, the instruction immediately following the one that initiated idle mode is executed. note only external interrupts can be used to release stop mode. to release idle mode, you can use either type of interrupt (internal or external). 0.1-10 m f internal recommand external circuit 200 k w figure 8-1. reset circuit application
s3c880a/f880a n reset and power-down 8 - 7 f programming tip ? enter to stop mode the following sample program shows you recommended entering stop mode for the s3c880a/f880a. ld stcon, #10100101b ; after this instruction is executed ; stop instruction is available stop nop ; nop need more than three after stop instruction nop nop stop available state stcon #10100101b ston instruction stop state enable disable enable disable stop available state is released automatically after stop instruction. figure 8-2. stop state timing diagram
n reset and power-down s3c880a/f880a 8 - 8 f programming tip ? initial settings for address space, vectors, and peripherals the following sample program shows you recommended initial settings for the s3c880a/f880a address space, interrupt vectors, and peripheral functions. program comments guide you through the required steps: osd_reg equ 0c8h ; osd working register area osd_flg equ 8 dsp_typ equ 9 vramad equ 0ch work1 equ 0bh ; general-purpose area work2 equ 0ah ; general-purpose area remocon equ 3fh ; capa data save register org 0 2 h dw capa_int ; capture a interrupt org 0b e h dw timera_int ; timer a interrupt org 0c0h dw p 10 _int ; p 1.0 external interrupt dw p 11 _int ; p 1.1 external interrupt dw osd row _int ; osd row interrupt dw p 12 _int ; p 1.2 external interrupt dw p 13 _int ; p 1.3 external interrupt org 0d4h dw v_sync_int ; v-sync inte rrupt org 0f c h dw timer0_int ; timer 0 interrupt org 0100h start di ; disable all interrupts ld btcon,#0aah ; disable the watchdog timer ld clkcon,#98h ; non-divided clock clr sym ; disable global and fast interrupts clr spl ; stack pointer low byte ? "0" ; stack area will start at 0ffh sb1 ; select bank 1 (continued on next page)
s3c880a/f880a n reset and power-down 8 - 9 f programming tip ? initial settings for address space, vectors, and peripherals (continued) ; enable osd row interrupt ld htcon,# 2 ah ; enable v-sync interrupt ld dspcon,#0a0h ; disable osd logic sb0 ; select bank 0 ld pwmcon,#0e9h ; prescaler ? 4 ; enable pwm counter ; enable capture a interrupt ld ipr,#0aeh ; interrupt priority settings ; irq6 > 7 > 3 > 2 > 0 > 1 ld imr,#0c c h ; enable level 2, 3, 6, and 7 interrupts ld p0conh,#00h ; in put mode ld p0conl,#0ffh ; push-pull output mode ld p1conh,#0ffh ; output mode ld p1conl,#00h ; input mode ld p2conh,#00h ; input mode ld p2conl,#00h ; input mode ld p3conl,#00h ; input mode ld tacon,#54h ; prescaler ? 6 ; clock source ? cpu clock / 1000 ; enable timer a interrupt ; interval timer mode ld tadata,#03h ; 4-millisecond interrupt ei main nop nop nop jp t,main ; jump main capa_int: ; capa interrupt service push pp ; save page pointer to stack push rp0 ; save register pointer 0 to stack push rp1 ; save register pointer 1 to stack ld remocon,capa ; remocon ? capa data pop rp1 ; restore register pointer 1 value pop rp0 ; restore register pointer 0 value pop pp ; restore page pointer value iret ; return from interrupt service routine (continued on next page)
n reset and power-down s3c880a/f880a 8 - 10 f programming tip ? initial settings for address space, vectors, and peripherals (continued) timera_int push pp ; timer_a interrupt service push rp0 push rp1 ld tacon, #54h ; clear pending bit pop rp1 pop rp0 pop pp iret ; return from interrupt service routine v_sync_int push pp ; v_sync interrupt service push rp0 push rp1 sb1 ld htcon, # 3a h ; clear pending bit pop rp1 pop rp0 pop pp iret ; return from interrupt service routine osd row_int: push pp push rp0 push rp1 sb1 ld htcon, #2bh ; clear pending bit pop rp1 pop rp0 pop pp iret p 10 _int: ; p 1.0 external interrupt p11_int: ; p1.1 external interrupt p 12 _int: ; p 1.2 external interrupt p13_int: ; p1.3 external interrupt timer0_int: ; timer 0 interrupt iret ; return from interrupt service routine
s3c880a/f880a i/o ports 9 - 1 9 i/o ports overview the s3c880a/f880a and the s3c880a/f880a microcontroller s have four i/o ports with a total of 26 pins. up to 10 pins can be configured as n -channel open-drain outputs. of these 10 open-drain pins, 6 pins can withstand loads of up to 6 volts and 4 pins can withstand loads of up to 5 volts. the cpu accesses ports by directly writing or reading port registers. no special i/o instructions are required. table 9 - 1 gives you a summary of port functions: table 9 - 1. s3c880a/f880a port configuration overview port configuration options programmability 0 general i/o port , configurable for digital input or push-pull output. pins p0.6?p0.7 are multiplexed to support alternative function. bit programmable 1 general i/o port , configurable for digital input or n-channel open-drain output. pins 1. 0 ?p1. 5 can withstand up to 6-volt loads. pins 1.0?p1.3 are multiplexed to support alternative functions. bit programmable 2 general i/o port , configurable for n-channel open-drain or push-pull output mode by software. p ins can withstand up to 5-volt loads. each pin has an alternative function. bit programmable 3 general 2 -bit i/o port, configurable for digital input or n -channel open-drain output. pins can withstand up to 5 v . p3.0?p3. 1 can be alternate ly used as external interrupt inputs adc0?adc1 . bit programmable
i/o ports s3c880a/f880a 9 - 2 port data registers data registers for ports 0?3 have the structure shown in figure 9 -1 . table 9 - 2 gives you an overview of the port data register locations: table 9 - 2. port data register summary register name mnemonic decimal hex location r/w port 0 data register p0 224 e0h set 1, bank 0 r/w port 1 data register p1 225 e1h set 1, bank 0 r/w port 2 data register p2 226 e2h set 1, bank 0 r/w port 3 data register p3 227 e3h set 1, bank 0 r/w i/o port n data register (n = 0-3) lsb msb .7 .6 .5 .4 .3 .2 .1 .0 pn.0 pn.4 pn.1 pn.2 pn.3 pn.7 pn.5 pn.6 figure 9 - 1. port data register format port 0 port 0 is a bit-programmable general i/o port. port 0 is accessed directly by writing or reading the port 0 data register, p0 (e0h, set 1, bank 0). the port 0 pins are configured by bit-pair settings in the p0conh and p0conl registers. p0conh controls i/o for the upper byte pins and p0conl controls i/o for the lower byte pins.
s3c880a/f880a i/o ports 9 - 3 port 0 control register, high byte (p0conh) e4h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p0.7/adc2 p0.6/adc2 p0.4 p0.5 p0conh pin configuration settings: 00 01 10 11 input mode input mode (p0.4-p0.5), adc input mode (p0.6-p0.7) push-pull output mode (p0.4-p0.5), open-drain output mode (p0.6-p0.7) push-pull output mode (p0.4-p0.5), open-drain output mode (p0.6-p0.7) figure 9 - 2. port 0 high-byte control register (p0conh) port 0 control register, low byte (p0conl) e5h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p0.3 p0.2 p0.1 p0.0 p0conl pin configuration settings: 00 01 10 11 input mode input mode n-channel open-drain output mode (5v load capacity) push-pull output mode figure 9 - 3. port 0 low-byte control register (p0conl)
i/o ports s3c880a/f880a 9 - 4 port 1 port 1 is a bit-programmable general i/o port. port 1 is accessed directly by writing or reading the port 1 data register, p1 (e1h, set 1, bank 0). the upper byte (p1.4?p1.7) and the lower byte (p1.0?p1.3) are controlled by the p1conh and p1conl registers, respectively. p1conh is located at e6h in set 1, bank 0 and p1conl is located at e7h in set 1, bank 0. port 1 control register, high byte (p1conh) e6h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p1.4 p1conh pin configuration settings: 00 01 10 11 input mode inputmode (p1.4-p1.6), timer 0 clock input: t0ck (p1.7) p1.4-p1.5: n-channel open-drain mode (6v load capacity), p1.6-p1.7: push-pull output mode p1.4-p1.5: n-channel open-drain mode (6v load capacity), p1.6-p1.7: push-pull output mode p1.5 p1.6 p1.7/t0ck figure 9 - 4. port 1 high-byte control register (p1conh) port 1 control register, low byte (p1conl) e7h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p1.0/int0 p1conl pin configuration settings: 00 01 10 11 input mode: interrupt disabled input mode: interrupt on rising edge input mode: interrupt on falling edge n-channel open-drain output mode (6v load capacity) p1.1/int1 p1.2/int2 p1.3/int3 figure 9 - 5. port 1 low-byte control register (p1conl)
s3c880a/f880a i/o ports 9 - 5 port 2 port 2 is a bit-programmable general i/o port. port 2 is accessed directly by writing or reading the port 2 data register, p2 (e2h, set 1, bank 0). the upper byte (p2.4?p2.7) and the lower byte (p2.0?p2.3) are controlled by the p2conh and p2conl registers, respectively. a reset clears the port 2 control registers to '00h', configuring the port 2 pins to normal input mode (p2.0?p2.3) and input mode (2.4?p2.7) . you use p2conh and p2conl register settings to configure individual port 2 pins: port 2 control register, high byte (p2conh) e8h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p2.4/pwm4 p2conh pin configuration settings: 00 01 10 11 input mode n-channel open-drain output mode (5v load capacity) push-pull output mode p2.4: pwm4 output mode (open-drain type) p2.5: pwm5 output mode (push-pull circuit type) p2.6: timer 0 output mode (pwm or interval; open-drain type) p2.7: osd half-tone output mode (push-pull circuit type) p2.5/pwm0 p2.6/t0 p2.7/osdht figure 9 - 6. port 2 high-byte control register (p2conh) port 2 control register, low byte (p2conl) e9h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p2.0/pwm5 p2conl pin configuration settings: 00 01 10 11 normal input mode n-channel open-drain output mode with 5v load capacity pwm output mode: n-channel open-drain type push-pull output mode p2.1/pwm1 p2.2/pwm2 p2.3/pwm3 figure 9 - 7. port 2 low-byte control register (p2conl)
i/o ports s3c880a/f880a 9 - 6 port 3 port 3 is a bit-programmable general i/o port. only two bits are used. port 3 is accessed directly by writing or reading the port 3 data register, p3 (e3h, set 1, bank 0). a reset operation sets the p3 data register to ' 00h', and the port 3 control register to ?0fh?, configuring the port 3 pins to output (open-drain) mode. port 3 control register (p3con) ebh, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p3.0/adc0 p3con pin configuration settings: 00 01 10 11 input mode adc input mode input mode n-channel open-drain output mode (with 5v load capacity) p3.1/adc1 no effect figure 9 -8 . port 3 control register (p3con)
s3c880a/f880a i/o ports 9 - 7 f programming tip ? configuring i/o port pins to specification the following sample program shows you how to configure the s3c880a/f880a i/o ports to specification. the following parameters are given for ports 0, 1, 2, and 3: ? set p0.0 and p0.1 to inp ut mode ? set p0.2 and p0.3 to output mode ? set p0.4 and p0.5 to input mode ? set p0.6 and p0.7 to open-drain output mode ? set p1.0 ?p1. 1 to interrupt rising edge mode ? set p1. 2?1.5 to open-drain output mode ? set p1.6 ? p1.7 to push-pull output mode ? set p2.0 and p2.1 to open-drain output mode ? set p2.2 ?p2. 4 to input mode ? set p2.6 ?2.7 to push-pull output mode ? set p2. 5 to pwm 0 output mode ? set p3.0 ?p3. 1 to adc input mode sb0 ; select bank 0 ld p0conh,#0f 0 h ; p0.4, p0.5 ? input mode ; p0.6, p0.7 ? o pen-drain outp ut mode ld p0conl,#0f0h ; p0.0, p0.1 ? input mode ; p0.2, p0.3 ? outp ut mode ld p1conh,# 0ff h ; p1. 6?1.7 ? push-pull output mode ; p1. 2?1.5 ? open-drain output mode ld p1conl,#0 f5 h ; p1.0 , p1. 1 ? interrupt rising edge mode ld p2conh,#0 ac h ; p2.4 ? input mode ; p2.6 , 2.7 ? push-pull output mode ; p2. 5 ? pwm 0 output mode ld p2conl,#0 5 h ; p2.0, p2.1 ? open-drain output mode ; p2.2 , p2.3 ? input mode ld p3conl,#0 5 h ; p3.0 , p3. 1 ? adc input mode
i/o ports s3c880a/f880a 9 - 8 f programming tip ? clearing port 0 interrupt pending bits this sample program shows you how to clear the interrupt pending bits for port 1 . the program parameters are as follows: ? enable only the interrupt level 1 (irq1) for p 1.0 ?p 1.1 ? set the interrupt priorities as p 1.0 > p 1.1 org 0c0h vector ext_int_p 10 vector ext_int_p11 org 0100h nreset di ; disable all interrupts sb0 ; select bank 0 ld btcon,#0aah ; disable the watchdog timer ld clkcon,#98h ; non-divided clock clr spl ; stack pointer low byte ? "0" ; stack area starts at 0ffh ld imr,#06h ; enable irq1 and irq2 interrupts ld ipr,#11h ; irq1 > irq2 ld p 1 conl,#0 a h ; p 1.0 , p 1 .1 ? input mode; falling edge interrupts srp #0c0h ; set register pointer to 0c0h ei ; enable interrupts main nop nop jp t,main (continued on next page)
s3c880a/f880a i/o ports 9 - 9 f programming tip ? clearing port 1 interrupt pending bits (continued) ext_int_p 10 : ; p 1.0 external interrupt service push pp ; save page pointer to stack push rp0 ; save register pointer 0 to stack push rp1 ; save register pointer 1 to stack pop rp1 ; restore register pointer 1 value pop rp0 ; restore register pointer 0 value pop pp ; restore page pointer value iret ; return from interrupt service routine ext_int_p 11 : ; p 1.1 external interrupt service push pp push rp0 push rp1 pop rp1 pop rp0 pop pp iret
i/o ports s3c880a/f880a 9 - 10 notes
s3c880a/f880a basic timer and timer 0 10 - 1 10 basic timer and timer 0 module overview the s3c880a/f880a microcontrollers have two default timers: an 8-bit basic timer (bt) and an 8-bit general-purpose timer/counter, called timer 0 (t0) . the basic timer (bt) has two alternative functions: 1) i t can be used as a watchdog timer that provide s an automatic reset mechanism in the event of a system malfunction, and 2) i t can be used to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the components of the basic timer are: ? clock frequency divider (f osc divided by 4096, 1024, or 128) with multiplexer ? 8-bit basic counter, btcnt (set 1, bank 0, fdh, read-only) ? basic timer control reg ister, btcon (set 1, d3h, read/write) ? clock frequency divider (f osc divided by 4096, 256, or 8) with multiplexer ? 8-bit counter (t0cnt), 8-bit comparator, and 8-bit reference data register (t0data) ? timer 0 match interrupt (t0int) generation ? timer 0 control register, t0con (set 1, d2h, read/write)
basic timer and timer 0 s3c880a/f880 a 10 - 2 basic timer control register (btcon) the basic timer control register, btcon, is used to sel ect the input clock frequency, clear the basic timer counter and frequency dividers, and enable or disable the watchdog timer function. it is located in set 1, address d3h, and is read/write addressable using register addressing mode only. a reset clears btcon to '00h'. this enables the watchdog function and selects a basic timer clock frequency of f osc /4096. to disable the watchdog function, you must write the signature code '1010b' to the basic timer register control bits btcon.7?btcon.4. the 8-bit basic timer counter, btcnt (set 1, bank 0, fdh), can be cleared during the normal operation by writing a "1" to btcon.1. to clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you should write a "1" to btcon.0. basic timer control register (btcon) d3h, set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 divider clear bit for basic timer and t0: 0 = no effect 1 = clear divider basic timer counter clear bit: 0 = no effect 1 = clear basic timer counter basic timer input clock selection bits: 00 = fosc/4096 01 = fosc/1024 10 = fosc/128 11 = fosc/16 watchdog timer enable bit: 1010b = disable watchdog function other value = enable watchdog function figure 10 - 1. basic timer control register (btcon)
s3c880a/f880a basic timer and timer 0 10 - 3 basic timer function description watchdog timer function the basic timer overflow signal can be programmed to generate a reset by setting the btcon.7?btcon.4 bits to any value other than '1010b'. (the '1010b' value disables the watchdog function.) a reset clears the btcon register to '00h', automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the clkcon register setting) divided by 4096 as the bt clock. with every overflow of the basic timer counter, a reset occurs. during the normal operation, this overflow-generated reset should be prevented from occurring. to do this, the basic timer counter value must be cleared by software (write btcon.1 to "1") in regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the basic timer counter clear operation may not be executed and a basic timer overflow will occur, initiating a system reset. in other words, in normal operating condition the basic timer overflow loop (a bit 7 overflow of the 8-bit bt counter) is always broken by a clear counter instruction. an application program can use the basic timer as a watchdog timer to trigger an automatic system reset in case a malfunction occurs. oscillation stabilization interval timer function the basic timer determines the oscillation stabilization interval after a reset or the release of stop mode by an external interrupt. whenever a reset or an external interrupt occurs during stop mode, the oscillator begins operating. the basic timer value then starts increasing at the rate of f osc /4096 (in the case of a reset), or at the rate of the preset clock source (in the case of an external interrupt). when bit 4 of the bt counter is set to ?1? , a signal is generated to indicate that the stabilization interval has elapsed. this allows the clock signal to be gated on to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode a power-on reset or an external interrupt occurs to trigger a stop mode release, and oscillation starts. 2. if a power-on reset occurr s , the basic timer counter increase s at the rate of f osc /4096. if an external interrupt is used to release stop mode, the basic timer value increase s at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows. 4. when bit 4 of btcnt is set to ?1? , the normal cpu operation resumes.
basic timer and timer 0 s3c880a/f880 a 10 - 4 oscillation stabilization time normal operating mode 0.8 v dd t wait = (4096x16)/f osc basic timer increment and cpu operations are idle mode 10000b 00000b reset release voltage note: duration of the oscillator stabilization wait time, t wait , when it is released by a power-on-reset is 4096 x 16/f osc . t rst rc (r is external resistor and c is on chip capacitor) v dd reset internal reset release oscillator (x out ) btcnt clock btcnt value oscillator stabilization time trst ~ rc ~ ~ ~ 0.8 v dd figure 10-2. oscillation stabilization time on nreset
s3c880a/f880a basic timer and timer 0 10 - 5 note: duration of the oscillator stabilzation wait time, t wait , it is released by an interrupt is determined by the setting in basic timer control register, btcon. v dd oscillation stabilization time reset external interrupt oscillator (x out ) btcnt clock btcnt value t wait basic timer increment 10000b stop release signal 00000b normal operating mode normal operating mode stop mode stop mode release signal stop instruction execution btcon.3 btcon.2 0 0 1 1 0 1 0 1 t wait (4096 x 16)/fosc (1024 x 16)/fosc (128 x 16)/fosc invalid setting t wait (when f osc is 8 mhz) 10.92 ms 2.7 ms 0.341 ms figure 10-3. oscillation stabilization time on stop mode release
basic timer and timer 0 s3c880a/f880 a 10 - 6 timer 0 control register (t0con) the timer 0 control register, t0con, is used to select the timer 0 operating mode (interval timer) and input clock frequency, clear the timer 0 counter, and enable the t0 match interrupt. it also contains a pending bit for t0 match interrupt. it is located in set 1, address d2h, and is read/write addressable using r egister addressing mode. a reset clears t0con to '00h'. this sets timer 0 to normal interval timer mode, selects an input clock frequency of f osc /4096, and disables the t0 match interrupt. the t0 counter can be cleared at any time during the normal operation by writing a "1" to t0con.3. to enable the t0 match interrupt (t0int, irq0, vector fch), you must set t0con.1 to "1". the interrupt service routine must clear the pending condition by writing a "0" to the t0 interrupt pending bit, t0con.0. timer 0 control register (t0con) d2h, set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 t0 interrupt pending bit: 0 = no t0 interrupt pending 0 = clear t0 pending bit (write) 1 = t0 interrupt is pending t0 counter clear bit: 0 = no effect 1 = clear the t0 counter (when write) t0 operation mode selection bits: 00 = interval mode 01 = pwm mode 10 = pwm mode 11 = pwm mode t0 input clock selection bits: 00 = fosc/4096 01 = fosc/256 10 = fosc/8 11 = external clock (t0ck) (max fosc/8) t0 interrupt enable bit: 0 = disable t0 interrupt 1 = enable t0 interrupt no effect figure 10 -4 . timer 0 control register (t0con)
s3c880a/f880a basic timer and timer 0 10 - 7 timer 0 function description t0 interrupts (irq0, vector fch) the t0 module can generate one interrupt: the timer 0 match interrupt (t0int). t0int is also in the level irq0, vector address: fch. the t0int pending condition must be cleared by software by writing a "0" to the t0con.0 pending bit. interval timer mode in interval timer mode, a match signal is generated when the counter value is identical to the value written to the t0 reference data register, t0data. the match signal generates a t0 match interrupt (t0int, vector fch) and then clears the counter. if, for example, you write the value '10h' to t0data, the counter will increment until it reaches '10h'. at this point, the t0 interrupt request is generated, the counter value is reset and counting resumes. clk counter r (clear) comparator data register match pnd t0cnt interrupt enable/disable t0data irq0 (t0int) figure 10 -5 . timer 0 function diagram (interval timer mode)
basic timer and timer 0 s3c880a/f880 a 10 - 8 pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the t0 pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the t0 data register. in pwm mode, however, the match signal does not clear the counter (it runs continuously, overflowing at 'ffh', and continuing incrementing from '00h'). although it is possible to use the match signal to generate a t0int interrupt, an interrupt is typically not used in pwm-type applications . instead, the pulse at the t0 pin is held to low level as long as the reference data value is less than or equal to the counter value; the pulse is then held to high level for as long as the data value is greater than the counter value. one pulse width is equal to t clk x 256. (see figure 10-6) note: when timer 0 is configured to operate in pwm mode, interrupts are typically not used. clk counter comparator data register match pnd t0cnt interrupt enable/disable t0data irq0 (t0int) ctl t0con t0 pin high level when data > counter; low level when data < counter = figure 10- 6 . timer 0 function diagram (pwm mode )
s3c880a/f880a basic timer and timer 0 10 - 9 div div nreset or stop nreset data bus x in r 1/4096 1/1024 1/128 r 1/4096 1/8 1/256 bit 0 mux bit 3, 2 bit 1 bits 7, 6 btcnt 8-bit basic counter (read-only) overflow basic timer control register (write '1010xxxxb' to disable) mux t0ck t0cnt 8-bit counter (read-only) 8-bit comparator data bus ctl r match clear bit 3 bits 4, 5 t0data timer 0 data register (read/write) bit 3 t0 (pwm & interval) irq0 bit 3 interrupt enable data bus basic timer counter register timer 0 counter register note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter is set to "1"). figure 10 -7 . basic timer and timer 0 block diagram
basic timer and timer 0 s3c880a/f880 a 10 - 10 f programming tip ? configuring the basic timer this example shows how to configure the basic timer to sample specifications: org 0100h nreset di ; disable all interrupts sb0 ; select bank 0 ld btcon,#0aah ; disable the watchdog timer ld clkcon,#98h ; non-divided clock clr sym ; disable global and fast interru pts clr spl ; stack pointer low byte ? "0" ; stack area starts at 0ffh srp #0c0h ; set register pointer ? 0c0h ei ; enable interrupts main ld btcon,#52h ; enable the watchdog timer ; basic timer clock: f osc /4096 ; clear basic timer counter nop nop jp t,main
s3c880a/f880a basic timer and timer 0 10 - 11 f programming tip ? configuring timer 0 this sample program sets timer 0 to interval timer mode, determining the frequency of the oscillator clock, and the execution sequence which follows a time r 0 interrupt. the program given s are as follows: ? timer 0 is used in interval mode; the timer interval is set to 4 milliseconds ? oscillation frequency is 6 mhz ? general register 60h (page 0) ? 60h + 61h + 62h + 63h + 64h (page 0) is executed after a timer 0 interrupt org 0fch ; timer 0 interrupt (match ) vector t0int org 0100h nreset di ; disable all interrupts sb0 ; select bank 0 ld btcon,#0aah ; disable the watchdog timer ld clkcon,#98h ; non-divided clock clr sym ; disable global and fast interrupts clr spl ; stack pointer low byte ? "0" ; stack area starts at 0ffh ld t0con,#42h ; 01000010b ; input clock is f osc /256 ; interval timer mode ; enable the timer 0 interrupt ld t0data,#5dh ; set timer interval to 4 milliseconds ; (6 mhz/256) (93 + 1) = 0.25 k hz (4 ms) srp #0c0h ; set register pointer ? 0c0h ei ; enable interrupts t0int push pp ; save page pointer to the stack push rp0 ; save rp0 to stack sb0 ; select bank 0 ld pp,#00h ; page pointer ? 00h (select page 0) srp0 #60h ; rp0 ? 60h inc r0 ; r0 ? r0 + 1 add r2,r0 ; r2 ? r2 + r0 adc r3,r2 ; r3 ? r3 + r2 + carry adc r4,r0 ; r4 ? r4 + r0 + carry cp r0,#32h ; 50 4 = 200 ms jr ult,no_200ms_set bits r1.2 ; bit setting (61.2h) no_200ms_set: ld t0con,#42h ; clear pending bit pop rp0 ; restore register pointer 0 value pop pp ; restore page pointer value iret ; return from interrupt service routine
basic timer and timer 0 s3c880a/f880 a 10 - 12 notes
s3c880a/f880a timer a 11 - 1 11 timer a overview the s3c880a/f880a microcontrollers have an 8-bit timer/counter ( timer a ) . each timer has a control register, an 8 -bit counter register, an 8 -bit data register, an 8 -bit comparator. tim er a run s continuously. counter register addresses are not mapped and they cannot, therefore, be read or written. timer clock input timer a ha s different clock input options. y ou can select the non-divided cpu clock or the cpu clock divided by 1000. the selected clock input frequency for each timer can be scaled using the 4 -bit prescaler that is located in bits 4?7 of the tacon register. timer a interrupt control timer a generate a match signal when the count value is equal to the referenced data value in the tadata. when the interrupt enable bit is set for timer a, an interrupt is generated whenever a match is detected. the corresponding count register is then cleared and counting resumes. to enable the timer a interrupt, you should set tacon.2 to "1". the timer a interrupt pending bit is tacon.1. when a timer a pending bit read operation shows a "0" value, no interrupt is pending; when it is "1", an interrupt request is pending. when the request is acknowledged by the cpu and the service routine starts, the pending bit must be cleared by the interrupt service routine. to do this, you must write a "0" to the appropriate bit location.
timer a s3c880a/f880a 11 - 2 timer a function description when a match occurs, the timer is reset to zero. cpu clk ta counter comparator tadata match pnd r tacon.2 tacon.1 timer a interrupt (irq6,beh) 4-bit prescaler m u x tacon.3 1 + 1000 8-bit 8-bit figure 11 - 1. timer a block diagram
s3c880a/f880a timer a 11 - 3 timer a control register (tacon) the timer a control register, tacon, is located at f2h in set 1, bank 0. all bits are read/write addressable. the tacon register settings control four functions: ? interrupt enable/disable ? interrupt pending control (read for status, write to clear) ? clock source selection ? prescaler (4-bit) for timer clock input tacon.1 is the pending flag for the timer a interrupt (irq6, vector beh). application software can poll the taip bit to detect timer a interrupt requests. when an interrupt request is acknowledged, the interrupt service routine must clear tacon.1 by writing a "0" to the bit location. note that there are two clock source selections for timer a: the cpu clock divided by 1000 or the non-divided cpu clock. a reset clears tacon to '00h', selecting the cpu clock/1000, and disabling the timer a interrupt. timer a control register (tacon) f2h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 not used timer a interrupt pending bit: 0 = no interrupt pending (when read) 0 = clear pending bit (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) 4-bit prescaler for timer a clock divide input by 1 (non-divided) divide input by 2 0000 0001 divide input by 3-15 1111 timer a interrupt enable: 0 = disable interrupt 1 = enable interrupt timer a clock source selection bit: 0 = cpu clock divided by 1000 1 = non-divided cpu clock figure 11 - 2. timer a control register (tacon)
timer a s3c880a/f880a 11 - 4 f programming tip ? configuring timer a this example sets timer a to normal interval mode , determining the oscillation frequency of the timer clock, the execution sequence that follows a timer a interrupt. the program parameters are: ? t he timer interval is set to 10 milliseconds ? oscillation frequency = 6 mhz ? general register 70h (page 0) ? 70h + 71h + 72h + 73h + 74h (page 0) is executed after a timer a interrupt org 0beh ; timer a interrupt vector taint org 0100h nreset di ; disable all interrupts sb0 ; select bank 0 ld btcon,#0aah ; disable the watchdog timer ld clkcon,#98h ; non-divided clock clr sym ; disable global and fast interrupts clr spl ; stack pointer low byte ? "0" ; stack area starts at 0ffh ld tacon,#54h ; 01010100b ; ps ? 5 (divide-by-6) ; cpu clock/1000 ; select interval mode for timer a ld tadata,#59h ; 10-ms interval time ; (6 mhz/1000) (59 + 1) = 100 hz (10 ms) srp #0c0h ; set register pointer ? 0c0h ei ; enable interrupts taint push pp ; save page pointer to stack push rp0 ; save register pointer 0 to stack sb0 ; select bank 0 ld pp,#00h ; page pointer ? 00h (select page 0) srp0 #70h ; rp0 ? 70h inc r0 ; r0 ? r0 + 1 add r2,r0 ; r2 ? r2 + r0 adc r3,r2 ; r3 ? r3 + r2 + carry adc r4,r0 ; r4 ? r4 + r0 + carry cp r0,#64h ; 100 10 ms = 1000 ms (1 second) jr ult,no_1sec_set bits r1.2 ; bit setting (7 1.2h) (continued on next page)
s3c880a/f880a timer a 11 - 5 f programming tip ? configuring timer a (continued) no_1sec_set: ld tacon,#54h ; clear pending bit pop rp0 ; restore register pointer 0 value pop pp ; restore page pointer value iret ; return from interrupt service routine
timer a s3c880a/f880a 11 - 6 notes
s3c880a/f880a pwm and capture 12- 1 12 pwm and capture pwm/capture module the s3c880a/f880a microcontrollers have two 14-bit pwm circuit s and four 8-bit pwm circuits. the 14-bit circuits are called pwm0 and pwm1; the 8-bit circuits are pwm2?pwm5. the operation of all the pwm circuit s is controlled by a single control register, pwmcon. pwmcon also contains a 3 -bit prescaler for adjusting the pwm frequency (cycle). the capture function, called capture a, is integrated in this block. using pwmcon settings, you can enable the capture a interrupt and select the desired triggering edge for data capture on the capa input pin. the pwm counter is a 14 -bit incrementing counter. it is used by the 14-bit pwm circuits. to start the counter and enable the pwm circuits, you must set pwmcon.5 to "1". if the counter is stopped, it retains its current count value; when re-started, it resumes counting from the retained count value. a 3 -bit prescaler controls the clock input frequency to the pwm counter. by modifying the prescaler value, you can divide the input clock by one (non-divided), two, three, four, five, six, seven, or eight . the prescaler output is the clock frequency of the pwm counter.
pwm and capture s3c880a/f880a 12- 2 pwm control register (pwmcon) the control register for the pwm module, pwmcon, is located at the register address f8h in set 1, bank 0. bit settings in the pwmcon register control the following functions: ? 3 -bit prescaler for scaling the pwm counter clock ? s top/start (or resume) the pwm counter operation ? capture a interrupt enable and capture a edge selection a reset clears all pwmcon bits to logic zero, disabling the entire pwm module. pwm control register (pwmcon) f8h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 capture function control bits: 00 = disable capture function 01 = capture on falling edges 10 = capture on rising edges 11 = capture on both edges 3-bit prescaler for pwm counter clock: non-divide divide by 2 divide by 3 divide by 4 divide by 5 divide by 6 divide by 7 divide by 8 not used pwm counter enable bit: 0 = stop counter 1 = start (resume) counting .4 .7 .6 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 capture interrupt enable bit: 0 = disable capture interrupt 1 = enable capture interrupt figure 12 - 1. pwm control register (pwmcon)
s3c880a/f880a pwm and capture 12- 3 pwm2?pwm5 the s3c880a/f880a microcontrollers have four 8-bit pwm circuits, called pwm2?pwm5. these 8 -bit circuits have the following components: ? 14-bit counter with 3-bit prescaler ? 8-bit comparators ? 8-bit pwm data registers (pwm2?pwm5) ? pwm output pins (pwm2?pwm5) the pwm2?pwm5 circuits are controlled by the pwmcon register (f8h, set 1, bank 0). cpu clk 8-bit pwm2-pwm5 registers 8 x 4 data bus 8-bit pwm2-pwm5 comparators x 4 8 lower 8-bit of 14-bit counter pwm0/1 logic "1" when reg > count "0" when reg < count = pwm2-pwm5 output pins pwm2-pwm5 output pins 3-bit p.s. pwmcon.5 upper 6-bit of 14-bit counter capture register 6 2 8 8 cap input pwmcon.1 pwmcon.0 pwmcon.3 irq3 (02h) data bus figure 12-2. block diagram for pwm2?pwm5
pwm and capture s3c880a/f880a 12- 4 pwm2?pwm5 function description all the four 8-bit pwm circuits function identically: each has its own 8-bit data register and 8-bit comparator. each circuit compares a unique data register value to the lower 8-bit value of the 14-bit pwm counter. the pwm2?pwm5 data registers are located in set 1, bank 1, at locations f8h?fbh, respectively. these data registers are read/write addressable. by loading specific values into the respective data registers, you can modulate the pulse width at the corresponding pwm output pins, pwm2?pwm5. the level at the output pins toggles high and low at a frequency equal to the counter clock, divided by 256 (2 8 ). the duty cycle of the pwm0 and pwm1 pins ranges from 0% to 99.6%, based on the corresponding data register values. to determine the pwm output duty cycle, its 8-bit comparator sends the output level high when the data register value is greater than the lower 8-bit count value. the output level is low when the data register value is less than or equal to the lower 8-bit count value. the output level at the pwm2?pwm5 pins remains at low level for the first 256 counter clocks. then, each pwm waveform is repeated continuously, at the same frequency and duty cycle, until one of the following three events occurs: ? the counter is stopped ? the counter clock frequency is changed ? a new value is written to the pwm data register
s3c880a/f880a pwm and capture 12- 5 staggered pwm outputs the pwm2?pwm5 outputs are staggered in order to reduce the overall noise level on the pulse width modulation circuits. if you load the same value to the pwm2?pwm5 data registers, a match condition (data register value is equal to the lower 8 -bit count value) will occur on the same clock cycle for all the four 8-bit pwm circuits. the output of pwm3, pwm4, and pwm5 are delayed by one-half of a counter clock for subsequent clock cycles (see figure 12-4). notes: 1. a counter clock value of 8 mhz is assumed for all timing values. 2. 'n' = 2-5, for pwm2-pwm5 counter value (hex) pwm = "0" 0h 125 ns 100h 12.5 m s 125 ns pwm cycle 25 m s 200h 300h counter clock (8 mhz) pwm = "1" pwmn = 80h pwmn = ffh figure 12-3. pwm waveforms for pwm2?pwm5
pwm and capture s3c880a/f880a 12- 6 pwm2 0h (after reset ) 100h cpu clock pwm3 pwm4 pwm5 match occurs; pwm2 toggles to high level 1/2-clock delay 1/2-clock delay 1/2-clock delay figure 12-4. pwm clock to pwm2?pwm5 output delays
s3c880a/f880a pwm and capture 12- 7 pwm0 ?pwm1 t he s3c880a/f880a pulse width modulation (pwm) module has two 14-bit pwm circuit s ( pwm0 and pwm1) . the 14-bit pwm circuits have the following components: ? 14 -bit counter with 3 -bit prescaler (an 8-bit counter with 6-bit extension is used for 14-bit output resolution) ? 8-bit comparator and extension cycle circui t ? 8-bit reference data registers (pwm0 , pwm1 ) ? 6-bit extension data registers (pwm0ex , pwm1ex ) ? pwm output pins (pwm0 , pwm1 ) the pwm0 and pwm1 circuits are enabled by the pwmcon register (f8h, set 1, bank 0). pwm counter the pwm counter is a 14 -bit incre asing counter comprised of a lower byte counter and an upper byte counter. to determine the pwm module's base operating frequency, the lower byte counter is compared to the pwm data register value. in order to achieve higher resolutions, the lower six bits of the upper byte counter can be used to modulate the "stretch" cycle. to control the "stretching" of the pwm output duty cycle at specific intervals, the 6 -bit extended counter value is compared with the 6-bit value (bits 2?7) that you write to the module's extension register. pwm data and extension registers two pwm (duty) data registers, located in set 1, bank 0, determine the output value generated by each 14-bit pwm circuit. pwm0 and pwm1 are read/write addressable. ? 8-bit data registers pwm0 (f4h) and pwm1(f6h) ? 6 -bit extension registers pwm0ex (f5h) and pwm1ex (f7h) of which only bits 2?7 are used to program the required pwm output, you should load the appropriate initialization values into the 8-bit data registers (pwm0 , pwm1 ) and the 6-bit extension registers (pwm0ex , pwm1ex ). to start the pwm counter, or to resume counting, you should set pwmcon.5 to "1". a reset operation disables all pwm output. the current counter value is retained when the counter stops. when the counter starts, counting resumes at the retained value. pwm clock rate the timing characteristics of both 14-bit output channels are identical, and are based on the maximum 8 -mhz cpu clock frequency. the 2-bit prescaler value in the pwmcon register determines the frequency of the counter clock . you can set pwmcon.6 and pwmcon.7 to divide the cpu clock frequency by 1 (non-divided), 2, 3, 4, 5, 6, 7, or 8. because the maximum cpu clock rate for the s3c880a/f880a microcontrollers is 8 mhz, the maximum base pwm frequency is 31.25 khz (8 mhz divided by 256). this assumes a non-divided cpu clock.
pwm and capture s3c880a/f880a 12- 8 table 12 - 1. pwm0 and pwm1 control and data registers register name mnemonic address (set 1, bank 0) function pwm0 data registers pwm0 f4h 8-bit pwm0 basic cycle frame value pwm0ex f5h 6-bit extension ("stretch") value pwm 1 data registers pwm 1 f6 h 8-bit pwm 1 basic cycle frame value pwm 1 ex f 7 h 6-bit extension ("stretch") value pwm control register pwmcon f8h pwm0 counter stop/start (resume), and 3 -bit prescaler for cpu clock; also contains capture a control settings pwm0 and pwm1 function description the pwm output signal toggles to low level whenever the lower 8-bit counter matches the reference value stored in the module's data register (pwm0 , pwm1 ). if the value in the pwm data register is not zero, an overflow of the lower counter causes the pwm output to toggle to high level. in this way, the reference value written to the data register determines the module's base duty cycle. the value in the 6-bit extension counter (the lower six bits of the upper counter) is compared with the extension settings in the 6-bit extension data register (pwm0ex , pwm1ex ). this 6-bit extension counter value (bits 2?7 ), together with extension logic and the pwm module's extension register, is then used to "stretch" the duty cycle of the pwm output. the "stretch" value is one extra clock period at specific intervals, or cycles (see table 12 - 2). if, for example, the value in the extension register is '1', the 32nd cycle will be one pulse longer than the other 63 cycles. if the base duty cycle is 50%, the duty of the 32nd cycle will therefore be "stretched" to approximately 51% duty. for example, if you write 80h to the extension register, all odd-numbered pulses will be one cycle longer. if you write fch to the extension register, all pulses will be stretched by one cycle except the 64th pulse. pwm output goes to an output buffer and then to the corresponding pwm0 and pwm1 output pin. in this way, you can obtain high output resolution at high frequencies. table 12 - 2. pwm output "stretch" values for extension registers pwm0ex and pwm1ex pwm0ex /pwm1ex bit "stretched" cycle number 7 1, 3, 5, 7, 9, ? , 55, 57, 59, 61, 63 6 2, 6, 10, 14, ? , 50, 54, 58, 62 5 4, 12, 20, ? , 44, 52, 60 4 8, 24, 40, 56 3 16, 48 2 32 1 not used 0 not used
s3c880a/f880a pwm and capture 12- 9 cpu clk 8-bit pwm2-pwm5 comparators lower 8-bit of 14-bit counter "1" when reg > count "0" when reg < count pwm0,pwm1 output pins 3-bit p.s. pwmcon.5 upper 6-bit of 14-bit counter extension logic 8 6-bit extension registers (pwm0ex, pwm1ex) 8-bit pwm2-pwm5 registers 8 match when reg = count bit 7 bit2 32 1, 3, ..., 61, 63 figure 12 -5 . block diagram for pwm0 and pwm1
pwm and capture s3c880a/f880a 12- 10 f programming tip ? programming pwm0 to sample specifications this example shows how to program the 14-bit pulse-width modulation module, pwm0. the program parameters are as follows: ? the oscillation frequency o f the main crystal is 6 mhz ? pwm0 data is in the working register r0 ? pwm0ex (pwm0 extension value) is in the working register r1, bits 2?7 the program performs the following operations: 1. set the pwm0 frequency to 23.437 khz 2. if r3.0 = "1", then pwm ? pwm + 12h (if an overflow occurs from r0, then r0 ? 0ffh and r1 ? 0fch.) 3. if r3.0 = "0", then pwm ? pwm ? 11h (if an underflow occurs from r0, then r0 ? 00h and r1 ? 00h.) n (0) pwmcon #20h r3.0 = 1? r1 r1 - #20h underflow? r1 r1 - #20h borrow? r1 r1 + #48h carry? r0 min. value r1 min. value carry? r0 r1 + #01h r0 max. value r1 max. value pwm control register setting y (1) n y y n n y y n pwm0ex r1 pwm0 r0 figure 12 -6 . decision flowchart for pwm0 programming tip
s3c880a/f880a pwm and capture 12- 11 f programming tip ? programming pwm0 to sample specifications (continued) ld pwmcon,#20h ; ps ? 0 (select 23.437-khz pwm frequency) ; enable the pwm counter btjrf pwm0_dec,r3.0 ; if r3.0 = "0", then jump to pwm0_dec pwm0_inc: add r1,#48h ; if r3.0 = "1", then add 48h to the pwm data jr nc,pwm0_data_end ; if no carry, go to pwm0_data_end inc r0 ; r0 ? r0 + 1 jr nz,pwm0_d ata_end ; if no overflow, jump to pwm0_data_end for update ld r0,#0ffh ; if overflow, set 0ffh to r0 ld r1,#0fch ; set 0fch to r1 jr t,pwm0_data_end ; jump to pwm0_data_end unconditionally pwm0_dec: sub r1,#44h ; r3.0 = "0", so subtract 44h from pwm data jp nc,pwm0_data_end ; if no borrow, jump to pwm0_data_end for update sub r0,#01h ; decrement r0 (r0 ? r0 ? 1) jr nc,pwm0_data_end ; if no borrow, jump to pwm0_data_end clr r0 ; clear data r0 clr r1 ; clear data r1 pwm0_data_end: ld pwm0e x,r1 ; load new value to pwm0ex (bits 2 ?7) ld pwm0,r0 ; load new value to pwm0
pwm and capture s3c880a/f880a 12- 12 capture unit an 8-bit capture unit is integrated in the pwm module. the capture unit detects incoming signal edges and can be used to measure the pulse width of the incoming signals. pwmcon register settings control the capture unit, which has the following components: ? 8-bit capture data register (capa) ? capture input pin (capa /pin 36) ? 8-bit capture interrupt (irq3, vector 02h) the capture unit captures the upper 8-bit value of the 1 4 -bit counter when a signal edge transition is detected at the capa pin. the captured value is then dumped into the capture a data register, also called capa, where it can be read. using pwmcon.0 and pwmcon.1 settings, you can set edge detection at the capa pin for rising edges, falling edges, or for both signal edge types. you can also use signal edges at the capa pin to generate an interrupt. pwmcon.3 is the capture a interrupt enable bit. the capture interrupt is in the level 3 (irq3) and its vector address is 02h. using the capture a interrupt, you can read the contents of the capa data register from edge to edge and use the values to calculate the elapsed time between pulses. cpu clk lower 8-bit of 14-bit counter pwmcon.5 upper 6-bit of 14-bit counter capture register 8 cap input pwmcon.1 pwmcon.0 pwmcon.3 irq3 (02h) data bus 3-bit p.s. 6 2 figure 12 -7 . block diagram for capture a
s3c880a/f880a pwm and capture 12- 13 f programming tip ? programming the capture module to sample specifications this example shows you how to program the s3c880a/f880a capture a module. the sample parameters are as follows: ? the main oscillator frequency is 6 mhz ? timer a interrupt occurs every 2 ms ? the following waveform is currently being input at the capture (cap a ) pin: t h t l ? the following registers are assigned for program values: register 70h ldr ; first captured count value register 71h ; second captured count value register 72h ; third capture d count value register 73h dwncnt ; down-counter; decremented by 1 with each ti mer a interrupt register 74h capcnt ; capture counter register 77h flag ; flags here is some additional information about the sample program: 1. if 4.35 ms < t h , t l < 4.6 ms, then set bit zero (ldr) in the register 77h; otherwise clear the zero bit (ldr) in the register 77h. 2. if the interval between two rising signal edges (capture trigger) is > 30 ms, disregard the capture setting. figures 12 -4 and 12 -5 show decision flowcharts for the sample program.
pwm and capture s3c880a/f880a 12- 14 y (zero) timer a setting capture unit setting dwncnt = 0? flag 0 capa rising enable main job n (not zero) main routine timer a interrupt back up the pp, pr0 dwncnt = 0? dwncnt dwncnt - #1h y (zero) other job restore pp, rp0 ret n (not zero) figure 12 -8 . decision flowchart (main routine and timer a interrupt)
s3c880a/f880a pwm and capture 12- 15 capture a interrupt save pp, rp0 flag = 0? "0" capcnt capcnt + 1 capcnt = #01? capcnt = #02? r2 3rd capture y (#02) flag "1" dwncnt #0fh capcnt #00h r0 1st capture capa interrupt on both edges sub r2, r1 sub r1, r0 r1 2nd capture 4.35 ms < r1 r2 < 4.6 ms ldr "1" ldr "0" capa disable n n y restore pp, rp0 "1" y (#01) ret figure 12 -9 . decision flowchart for capture a interrupt
pwm and capture s3c880a/f880a 12- 16 f programming tip ? programming the capture module to sample specifications ldr equ 0 dwncnt equ 3 capcnt equ 4 flag equ 7 clr pp ; select page 0 ld tacon,#54h ; ps ? 5, interval mode ; enable timer a interrupt ld tadata,#01h ; 2-ms interval (6 mhz /1000 6 2 = 0.5 khz = 2 ms) exec_main: srp0 #70h ; rp0 ? 70h cp rdwncnt,#00h ; down-counter = "0"? jp ne,main ; if not zero, then jump to main bitr r7.flag ; clear the 'flag' ld pwmcon,#0ah ; enable capture a interrupt ; trigger interrupt on rising edges main: ; other job... jp t,exec_main ; for looping taint push pp ; save page pointer push rp0 ; save register pointer 0 srp0 #70h ; rp0 ? 70h cp rdwncnt,#00h ; r3 (down-counter) = "0"? jp eq,ta_exec ; dec rd wncnt ; if not zero, then decrement r3 by 1 ta_exec: pop rp0 ; restore register pointer 0 pop pp ; restore page pointer iret ; return from ti mer a interrupt service routine (continued on next page)
s3c880a/f880a pwm and capture 12- 17 f programming tip ? programming the capture module to sample specifications (c ontinued ) capint push pp ; save the page pointer to stack push rp0 ; save register pointer 0 to stack srp0 #70h ; rp0 ? 70h inc rcapcnt ; increment the capture counter btjrt cap_one,r7.flag ; r7.flag ? "1", then jump to cap_one bits r7.flag ; set r7.flag clr rcapcnt ; clear capture counter ld rdwncnt,#0fh ; down-counter ? 15 (for counting 30 ms) ld r0,capa ; r0 ? 1st captured count value ; capa = 0f9h, page 0 ld pwmcon,#0bh ; enable capture interrupt ; trigger interrupt on both rising and falling edges cap_end pop rp0 ; restore the register pointer 0 value pop pp ; restore the page pointer value iret ; cap_one cp rcapcnt,#01h ; capcnt = #01h? jp ne,cap_con2 ; ld r1,capa ; r1 ? 2nd captured count value jr t,cap_end ; cap_con2 cp rcapcnt,#02h ; capcnt = #02h? jp eq,cap_con3 ; cap_con4 bitr r7.ldr ; clear the ldr bit in r7 cap_con5 ld pwmcon,#00h ; disable the capture module jr t,cap_end ; (continued on next page)
pwm and capture s3c880a/f880a 12- 18 f programming tip ? programming the capture module to sample specifications (c on clud ed ) cap_con3 ld r2,capa ; r2 ? 3rd capture count value sub r2,r1 ; r2 ? (3rd capture value ? 2nd capture value) sub r1,r0 ; r1 ? (2nd capture value ? 1st capture value) cp r1, #24h ; 24h = 4.6 ms jp ugt,cap_con4 ; if high signal period > 4.6 ms, then go to cap_con4 cp r2,#24h ; jp ugt,cap_con4 ; if low signal period > 4.6 ms, then go to cap_con4 cp r1,#22h ; 22h = 4.35 ms jp ult,cap_con4 ; if high signal period < 4.35 ms, then go to cap_con4 cp r2,#22h ; jp ult,cap_con4 ; if low signal period < 4.35 ms, then go to cap_con4 bits r7.ldr ; set bit 'ldr' jp t,cap_con5 ; jump to cap_con5 unconditionally
s3c880a/f880a on-screen display 13 - 1 13 on-screen display ( osd) overview the on-screen display (osd) module displays channel number, the time, and other information on a display screen. the osd character display module has 252 locations and supports a set of maximum 1024 characters. (two characters are reserved: 00h for the blank function and 01 h for the test pattern.) there are sixty four display colors. pattern generation software for application development using the s3c880a/f880a microcontrollers, samsung provides osd pattern generation software ( osdfont.exe ). you can customize standard osd patterns contained in this file. table 13 - 1. osd function block summary osd function block function description video ram (note) located in register page 1, the video ram contains 252 "word" lines. each line is 14 bits long. each 14 -bit ram address stores a n 10 -bit character code, a character halftone or character background color display control bit, and a 3-bit color code. video ram locations can be read or written: 00h?bfh can be accessed using any addressing mode; c0h?f b h can be accessed using indirect register or indexed addressing mode only. character rom the character rom contains an 18-dot 16-dot matrix data for 1024 characters. it is synchronized with the internal dot clock. the rom outputs the dot matrix data for each character. the function of two characters is pre-determined: 00h is used for blank (no-display) data and 01 h is for a factory test pattern. output control logic output control logic receives input from the character rom , osd control registers, and fade control circuits. it then decides what to display on the screen and what color the display should be. on the basis of truth table calculations, the final osd signals (blue, green, red, blank , and h/t ) are output from the osd block at pins 22?25, 21. note: the video ram can be cleared only by ?ld? instruction.
on-screen display s3c880a/f880a 13 - 2 internal osd clock red-green-blue (rgb) color outputs, as well as display rates and positions, are determined by the clock signal, dot_clk. this signal is generated by the l-c oscillator and is scaled by the dot and column counter. dot_clk equals the osd oscillator clock divided by the clock divider value. the clock divider value is set by the horizontal character size settings in the chacon register. the rate at which each new display line is generated is determined by h-sync input. the rate at which each new frame (screen) is generated is determined by v-sync input. for stable on screen display operation, the cpu clock frequency should faster than osd clock. osd video ram the osd video ram contains 2 52 word lines. each line is 1 4 bits long. of these 1 4 bits, eight are character display codes (bits 0 -9 ). bit 13 is the character halftone or character background color display control bit and bits 10-12 are used to determine the red, green, and blue components of the character color.
s3c880a/f880a on-screen display 13 - 3 register data bus register address bus xor xor polarity selector h-sync v-sync f osd row interrupt (irq2, 0c4h) line address (5) dot and column counter character generator rom (1024 x 18 x 16) output control logic character out (16-dot) dot clock line count (6) video ram (252 x 14 bits) char code (10) column address (5) row address (4) line and row counter rowint halfone (1) character color (3) red green blue blank halftone color buffer (5) figure 13 - 1. on-screen display function block diagram
on-screen display s3c880a/f880a 13 - 4 bit 3 h/t and bgrnd bit 2 r bit 1 g bit 0 b bit 4-5 vram h/t and bgrnd r g b character code (10-bit) h/t and bgrnd r g b character code (10-bit) h/t and bgrnd r g b character code (10-bit) h/t and bgrnd r g b character code (10-bit) row 0, column 0 row 0, column 1 row 0, column 2 row 0, column 3 00h = row 0, column 0 01h = row 0, column 1 fbh = row 11, column 20 color code vram (bit8-9) msb(bit 9) lsb(bit 0) 8-bit 6-bit data bus data bus color buffer (fch), bits 0-5 h/t and bgrnd r g b character code (10-bit) h/t and bgrnd r g b character code (10-bit) h/t and bgrnd r g b character code (10-bit) ~ ~ ~ ~ 10-bit 14-bit row 11, column 18 row 11, column 19 row 11, column 20 figure 13 - 2. on-screen display video ram data organization
s3c880a/f880a on-screen display 13 - 5 osd control register overview seven control registers are used to control specific functions of the on-screen display module: there are seven control registers for osd functions and one color buffer register: dspcon display control register chacon character size and fade control register fadecon fade control register rowcon row display position and inter-row spacing control register clmcon column display position and inter-column spacing control register colcon background color control register htcon halftone signal control register colbuf character color buffer register vsbcon v-sync blank time control register osdfrg1/2 fringe or border control registers osdsmh1/2 smooth display control registers osdcol osd factor control register osdfld field control register osdpltr1/2 palette color mode red 1/2 osdpltg1/2 palette color mode green 1/2 osdpltb1/2 palette color mode blue 1/2 these registers are described in this section within the context of the osd hardware module description. for detailed quick-reference descriptions of the control register bit settings, please refer to section 4, "control registers."
on-screen display s3c880a/f880a 13 - 6 display control register (dspcon) settings in the display control register, dspcon (f5h, set 1, bank 1), are used to enable and disable the on-screen display to select halftone or background color for character displays, choose the polarity for h-sync and v-sync signal synchronization, and as osd row counter which is read-only (bit4?bit7). display control register (dspcon) f5h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 display enable bit: 0 = disable osd (turn off l-c osc) 1 = enable osd (turn on l-c osc) halftone or background color selection bits (for character data in bit 13 of video ram): 00 = character background color 01 = not used 10 = halftone output 11 = character halftone and background color clock edge selection for h/v-sync polarity: 0 = rising edges 1 = falling edges osd row counter (read-only) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 row0 row1 row2 row3 row4 row5 row6 row7 row8 row9 row10 row11 1100-1111: not used figure 13 - 3. osd display control register (dspcon) note refer to the programming tip ? row interrupt function of 13-24.
s3c880a/f880a on-screen display 13 - 7 osd enable/disable the dspcon.0 setting enables or disables the on-screen display module. to enable the osd (turn l-c oscillation on), set dspcon.0 to "1"; to disable osd (turn l-c oscillation off), clear dspcon.0 to "0". when you do not use the display module, we recommend that you keep dspcon.0 cleared to "0" in order to reduce possible noise generation by the l-c oscillator. the dspcon.0 settings determine the on/off condition of l-c oscillation, synchronized with vsync input. and the osd output can be turned on or off in osd row units when l-c oscillation is on. at the point the value of dspcon.0 is changed from ?1? to ?0? in the middle of a frame, osd is disabled (osd output is off). in this condition, l-c oscillation becomes off at the next vsync input. when the value is shifted from ?0? to ?1?, osd is enabled (osd output is on) and l-c oscillation returns to ?on? at the following vsync input. h-sync and v-sync polarity selection dspcon.3 selects the triggering edge of h-sync and v -sync inputs to the osd block. incoming sync pulses enter a polarity option circuit that is controlled by the sync bit. if dspcon.3 = "0", rising edges are selected; if it is "1", falling edges are selected. character halftone or character background color selection dspcon.2 and dspcon.1 let you select a halftone or background color display for individual characters. (which characters are displayed as halftones, or with character background color, or with character halftone, or with character background color, or with character halftone and background color, depends on the bit 13 settings in the character video ram data) when dspcon.2-.1 = "00", the character background color option is selected; when dspcon.2-.1 = "10", the character halftone function is selected; when dspcon.2-.1 = "11", the character halftone and background color option are selected; but dspcon.2-.1 = "01" is not used. row counter function dspcon.4?dspcon.7 to the osd row read data. osd row counter indicates the osd row currently displayed. one row comprises one character (18 lines) and inter-row space (rowcon.2?.0). the row counter value for the first row after a vsync input is set to ?0?.
on-screen display s3c880a/f880a 13 - 8 character size control register (chacon) using the character size control register, chacon, you can specify four different standard character sizes in both vertical and horizontal directions. you also use the chacon register to select rows (0? 11 ) for the character fade function (see figure 13 -5 ). vertical character size is defined by bits 6 and 7 of the chacon register; horizontal direction is defined by bits 4 and 5. there are four basic character size settings: 1, 2, 3, and 4. size ' 1' is the smallest and ' 4' is the largest. for example, to display a ' 1' (horizontal) by ' 1' (vertical) size character, you sh ould clear chacon.4? chacon.7 to "0". to display a ' 4' by ' 4' size character, you sh ould set bits 4?7 to '1111b'. you can also combine different vertical and horizontal size selections to produce flattened or elongated characters (see figure 13 -5 ). "1 dot" is a minimum unit of character size. 1 character is composed of 16 dots in width and 18 dots in length. 1 dot in width is 1 fosd clock and 1 dot in length is 1 h-sync line. 1 dot of 1x1 character size (minimum unit) is composed of 1 fosd clock and 2 h-sync line (even + odd field). character size in width is increased by 1 clock. so x1, x2, x3, and x4 in width are the same as 1, 2, 3 and 4 clock, respectively. character size in length is increased by 2 h-sync line (even field + odd field), so x1 and x2 in length are the same as 2 h-sync line (even field + odd field) and 4 h- sync line (even field + odd field + even field + odd field), respectively. half dot in width is 1/2 fosd clock, and 1/2 dot in length is 1 h-sync line (even or odd field). in the fringe and boarder function, 1/2 dot setting can be used. so, please be more careful in using the 1/2 dot to prevent the blink. (because the character size is changed in 1 dot unit or set to 1/2 dot in fringing or boarder function, blinking can occur in interlace scan, so care must be taken when 1/2 dot is used for width.) osd character size control register (chacon) f0h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 vertical character size selection bits: 00 = 'x1' size 01 = 'x2' size 10 = 'x3' size 11 = 'x4' size fade row address selection bits: 0000 = row 0 0110 = row 6 0001 = row 1 0111 = row 7 0010 = row 2 1000 = row 8 0011 = row 3 1001 = row 9 0100 = row 4 1010 = row 10 0101 = row 5 1011 = row 11 horizontal character size selection bits: 00 = 'x1' size 01 = 'x2' size 10 = 'x3' size 11 = 'x4' size figure 13 -4 . osd character size control register (chacon)
s3c880a/f880a on-screen display 13 - 9 horizontal = x3 vertical = x2 horizontal = x2 vertical = x3 horizontal = x1 vertical = x1 horizontal = x4 vertical = x4 horizontal = x3 vertical = x3 horizontal = x2 vertical = x2 figure 13 -5 . osd character sizing dimensions
on-screen display s3c880a/f880a 13 - 10 fade-in and fade-out control register (fadecon) the osd block lets you program fade-in and fade-out displays. a fade-in display is one in which a character matrix is displayed incrementally until the complete character "appears". a fade-out display shows the complete character matrix first and then decrements the matrix line-by-line until the character "disappears" from the display field. the address of the character display (and the specific line) to be faded-in or faded-out is selected by writing bit values into the chacon and fadecon registers. bits 3?0 in the chacon register specify the 4-bit video ram address of one of the t welve rows (0 ?11 ) of the fade display. bits 0?4 in the fadecon register specify the 5-bit line address within the selected row. fade direction is controlled by fadecon.5. there are two choices of fade direction: before (fadecon.5 = "0") and after (fadecon.5 = "1"). when you select fade before , the character matrix is faded starting with line 0. when you select fade after , the matrix is faded starting with inter-row space line 6 . (the inter = row space line 6 start position is only a suggestion, however, as the fade interval is assignable by software.) to enable the fade function, you should set fadecon.6 to "1". (fadecon.7 is not used). note to avoid confusion in determining fade row and line addresses in the chacon and fadecon registers, please note that line is a horizontal value that encompasses the entire character display field while row is a horizontal value for the character display matrix. osd fade control register (fadecon) f1h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 fade function enable bit: 0 = fade disable 1 = fade enable fade row address selection bits: 00000 = line 0 00001 = line 1 00010 = line 2 00011 = line 3 00100 = line 4 00101 = line 5 00110 = line 6 00111 = line 7 01000 = line 8 01001 = line 9 01010 = line 10 01011 = line 11 01100 = line 12 01101 = line 13 01110 = line 14 01111 = line 15 10000 = line 16 10001 = line 17 10010 = inter-row space line 0 (1h) 10011 = inter-row space line 1 (2h) 10100 = inter-row space line 2 (3h) 10101 = inter-row space line 3 (4h) 10110 = inter-row space line 4 (5h) 10111 = inter-row space line 5 (6h) 11000 = inter-row space line 6 (7h) 11001-11111 = not used not used fade direction selection bit: 0 = fade before matrix 1 = fade after matrix figure 13 -6 . osd fade control register (fadecon)
s3c880a/f880a on-screen display 13 - 11 n n - 1 n + 1 line 12 13 14 15 16 17 18 (inter-row space line 0) 19 (inter-row space line 1) 20 (inter-row space line 2) 21 (inter-row space line 3) 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 8 9 0 1 2 3 4 5 6 7 18 (inter-row space line 0) 19 (inter-row space line 1) 20 (inter-row space line 2) 21 (inter-row space line 3) row figure 13 -7 . line and row addressing conventions when rowcon.2-.0 = "100"
on-screen display s3c880a/f880a 13 - 12 fade after (fade line = 13, fade line = no display) p q m n j k g h d e a b columns 0-20 rows 0-11 line = 0 line = 12 chacon fadecon 05h (fade row = 5) 6dh (fade line = 13; fade afte r selected) figure 13 -8 . osd fade function example: fade after
s3c880a/f880a on-screen display 13 - 13 p q columns 0-20 rows 0-11 line = 5 line = 17 fade before (fade line = 5, fade line = display) chacon fadecon 06h (fade row = 6) 45h (fade line = 5; fade b efore selected) m n j k g h d e a b figure 13 -9 . osd fade function example: fade before
on-screen display s3c880a/f880a 13 - 14 display position control the on-screen display has 2 52 character display positions. there are 2 1 horizontal columns and 1 2 vertical rows. positions can be numbered sequentially from 0?2 51 (decimal) or from 0? fb (hexadecimal), as shown in figures 13 - 11 and 13 -12 . to control display position, you can adjust the top and left margins and the inter-column and inter-row spacing between characters on the screen. columns 0-20 rows 0-11 decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 83 103 104 123 124 125 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 180 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 figure 13 - 1 0 . 2 52 -byte on-screen character display map (decimal) columns 0-20 rows 0-11 hexadecimal 0 1 2 3 4 5 6 7 8 9 a 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 83 b c d e f 10 1a 1b 1c 1d 1e 1f 2a 2b 2c 2d 2e 2f 3a 3b 3c 3d 3e 3f 4a 4b 4c 4d 4e 4f 5a 5b 5c 5d 5e 5f 6a 6b 6c 6d 6e 6f 7a 7b 7c 7d 7e 7f 8a 8b 8c 8d 8e 8f 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 d4 d5 d2 d3 d8 d9 d6 d7 da db de df dc dd e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb ef figure 13 - 1 1 . 2 52 -byte on-screen character display map (hexadecimal)
s3c880a/f880a on-screen display 13 - 15 row control register (rowcon) the row control register, rowcon, controls the top margin and inter-row spacing. top margin is the distance (in h- sync pulses) to the top row of a character display from the top edge of its display frame. inter-row spacing is the distance (in h-sync pulses) between two rows of displayed characters. the inter-row spacing value you select is applied equally to all rows in the display. osd row control register (rowcon) f2h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 inter-row spacing control bits (0h-7h in h-sync pulses): 000 = no inter-row spacing (0h) 001 = inter-row spacing = 1h 111 = inter-row spacing = 7h top margin display position control bits (4 x tmg value of 0-31 dots): 00000 = top margin = 0h 00001 = top margin = 4h 11111 = top margin = 124h figure 13 - 1 2 . osd row control register (rowcon) column control register (clmcon) the column control register, clmcon, controls the left margin and inter-column spacing. left margin is the distance to the character display from the left edge of the display frame. inter-column spacing is the distance (0?7 dots) between space separating the characters displayed in a row. the inter-column spacing value that you select is applied equally to all columns in the display. osd column control register (clmcon) f3h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 left margin display position control value (16 + 4 x lmg value of 0-31 dots): 00000 = left margin = 16 dots clock 00001 = left margin = 16 + 4 x 1 dot clock 11111 = left margin = 16 + 4 x 31 dot clock inter-column spacing control value (0-7 dots): 000 = no inter-column spacing 001 = inter-column spacing = 1 dot 111 = inter-column spacing = 7 dots figure 13 - 1 3 . osd column control register (clmcon)
on-screen display s3c880a/f880a 13 - 16 inter-row space inter-column space left margin top margin figure 13 - 1 4 . osd display formatting and spacing conventions calculating row and column spacing inter-row spacing and inter-column spacing are controlled by the rowcon and clmcon registers. you can select from zero to seven dots of spacing. for inter-row spacing, the desired spacing value (0?7) is written to bits 0?2 of the rowcon register. for inter- column spacing, the desired spacing value (0?7) is written to bits 0?2 of the clmcon register. calculating margin settings by writing a value to rowcon.3?rowcon.7, you can set the top margin at 4 the top margin dot value (tmg). because tmg is a 5-bit value, you can select any dot value in the range 0?31. by writing a value to clmcon.3?clmcon.7, you can set the left margin at 1 6 + 4 the left margin dot value (lmg). because lmg is a 5-bit value, you can select any dot value in the range 0?31. the zero position for the left margin is always 1 6 dots. ? top margin = 4 (top margin register value) h ? left margin = 1 6 + 4 (left margin register value) dot clock ? inter-column space = (register value) dot clock ? inter-row space = (register value) h
s3c880a/f880a on-screen display 13 - 17 character color control register (colbuf) the color of the character matrix display is controlled by manipulating a 5 -bit value in the osd video ram. you can modify the character color selection bits only by addressing the osd color buffer register, colbuf (f c h, set 1, bank 1). the color selection bits are colbuf.2 , colbuf.1, colbuf.0 and colbuf.3 (h/t and bgrnd) . these four bits comprise the rgb value (bit 10, 11, 12) and h/t and bgrnd enable bit (bit 13) of the character data stored in the video ram. when programming the display ram values for a character display, you must first load a 3-bit color value into the color buffer. this color setting is automatically appended to each 10 -bit character code as it is written to the osd ram addresses. if only one colbuf value is loaded, all characters in the screen display will, of course, be the same color. to change the display color of successive characters, modify the colbuf value before you load the address data for a specific row and column into the video ram. osd character color buffer (colbuf) fch, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 not used video ram bit 9 enable bit: 0 = disable vram bit 9 1 = enable vram bit 9 character color selection bits (.2 = red, .1 = green, .0 = blue) video ram bit 8 enable bit: 0 = disable vram bit 8 1 = enable vram bit 8 h/t and bgrnd enable bit: 0 = disable h/t and bgrnd 1 = enable h/t and bgrnd (vram bit 13) character color .0 osdcol.0 = 0 osdcol.0 = 1 .1 .2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 black blue green cyan red magenta yellow white color mode 0 color mode 1 color mode 2 color mode 3 color mode 4 color mode 5 color mode 6 color mode 7 figure 13 -15 . osd character color buffer register (colbuf)
on-screen display s3c880a/f880a 13 - 18 background color control the background color control register, colcon, lets you select background colors for both the display frame and characters: ? frame background is the full-screen display field upon which the character display is imposed. ? character background is a color field that surrounds the individual character. to enhance readability, the background is usually a color that contrasts or highlights the characters in a pleasing manner. frame background color wide screen color tv wide screen color tv character background color no character background color character background off wide screen color tv color tv wide screen wide screen color tv wide screen color tv figure 13 - 1 6. background color display conventions
s3c880a/f880a on-screen display 13 - 19 osd background color control register (colcon) f3h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 frame background color enable bit: 0 = disable frame background color (no color is displayed) 1 = enable frame background color character color selection bits (see table) character background color enable bit: 0 = disable character background color (no color is displayed) 1 = enable character background color frame background color selection bit: frame character background color .4 or .0 .5 or .1 .6 or .2 0 x osdcol.0 = 1 color mode 0 color mode 1 color mode 2 color mode 3 color mode 4 color mode 5 color mode 6 color mode 7 osdcol.0 = 0 black blue green cyan red magenta yellow white .7 or .3 x x 1 0 0 0 0 0 0 0 0 1 1 1 no background display 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 figure 13 - 1 7 . osd background color control register (colcon)
on-screen display s3c880a/f880a 13 - 20 v-sync blank control register (vsbcon) vsbcon sets the blank area, which stops the l-c oscillator during the defined time from the v-sync input time. unit of v-sync blank time is 1 h-sync. it can be set up to a maximum of 31 h-syncs. if vsbcon.4 is set from?0? to ?1001b?, blank time is always 9 h-syncs regardless of the setting value. v-sync blank control register (vsbcon) f7h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 v-sync blank time control bit: not used 00000 00001 00010 9 horizontal sync 9 horizontal sync 9 horizontal sync 01001 01010 01011 11110 11111 9 horizontal sync 10 horizontal sync 11 horizontal sync 30 horizontal sync 31 horizontal sync note: frame background is disabled during the v-sync blank time. figure 13 -18 . v-sync blank control register ( vsbcon )
s3c880a/f880a on-screen display 13 - 21 v-sync blank and top margin timing diagram the following is a timing diagram simplified with external v-sync input and h-sync input signals. v-sync blank and top margin are controlled by vsbcon and rowcon vsbcon .4?.0 = 01011b (v-sync blank time = 11 horizontal sync). rowcon.7?.3 = 00100b (top margin control value = 16, top margin = 5). v-sync blank v-sync blank time on chip row 0 v-sync interrupt row 0 interrupt v-sync input h-sync input internal v-sync h-line count 1 0 3 2 5 4 7 6 9 8 10 11 13 12 15 14 17 16 19 18 20 21 1 0 3 2 5 4 7 6 9 8 10 11 13 12 15 14 16 1 0 3 2 4 top margin rowcon.7-.3 (top margin control value) figure 13 -19 . v-sync blank and top margin timing diagram
on-screen display s3c880a/f880a 13 - 22 halftone signal control register (htcon) the halftone function lets you output halftone control signals to peripherals such as a chroma-ic. you can select halftone output for character back ground periods (as selected by bit 13 in the video ram) or for frame periods (regardless of the bit 13 setting). the halftone signal control register, htcon, has the following functions: ? halftone option selection (character or frame) ? halftone display enable/disable ? v-sync interrupt enable and pending control ? polarity selection of rgb and halftone outputs bits 4 and 5 are used for osd row interrupt function. osd row interrupt control the s3c880a/f880a has a total of 12 osd display rows. when enabled, an osd row interrupt occurs in the first line of each row. up to 12 osd row interrupts can be generated, while this number can be reduced according to different settings in top margin (rowcon.7?.3), inter row space (rowcon.2?.0), vertical character size (chacon.7?.6), and vsync blank time (vsbcon). the row counter of dspcon.7?.4 informs the order of an osd row interrupt occurring within a frame. an osd row interrupt is generated at the beginning of a row (for row0 through row11). osd row interrupt allow different controls to each row. if the osd control register is adjusted in the n-th row area, the new value is applied from (n+1)th row. that is, if the osd control register is adjusted in the first osd row interrupt (dspcon.7?.4 = 0000b) service routine, the new value is applied from row1. a change in the 12 th osd row interrupt service routine affects the rows from row0. note: osd output enable/disable (dspcon.0) settings are immediately applied. top margin (rowcon.7?.3) and vsbcon are applied in accordance with vsync input signals. halftone option selection in character periods only (htcon.2 = ?0?), the character specified in colbuf.3 may have the halftone function according to the condition of dspcon.2?.1 (dspcon.2?.1 = "10" or dspcon.2?.1 = "11"). in all frame periods (htcon.2 = ?1?), the entire section can have the function, regardless of the colbuf.3 condition.
s3c880a/f880a on-screen display 13 - 23 halftone signal control register (htcon) f3h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 halftone signal output polarity selection bit: (1) 0 = active high level 1 = active low level v-sync interrupt pending bit: 0 = no interrupt pending (when read) 0 = clear pending bit (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) v-sync interrupt enable bit: 0 = disable the v-sync interrupt 1 = enable the v-sync interrupt halftone option selection bit: (3) 0 = character back ground periods only (when bit 3 of colbuf is set to "1") 1 = all frame periods (disregard colbuf "bit 3") rgb polarity selection bit: (2) 0 = active high level 1 = active low level halftone control signal enable bit: 0 = disable halftone signal 1 = enable halftone signal osd row interrupt enable bit: 0 = disable the osd row interrupt 1 = enable the osd row interrupt osd row interrupt pending bit: 0 = no interrupt pending (when read) 0 = clear pending bit (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) notes: 1. the htcon.7 setting applies to halftone output only. the active high setting ("0") means that the normal halftone signal output is low level. when you select the active low setting ("1"), the normal halftone signal output is high level. 2. the active high setting ("0") for htcon.6 means that the normal rgb polarity is low level. when you select the active low setting ("1"), the normal rgb polarity is high level. 3. in case htcon.2 = 1, character halftone and background color (dspcon.2-.1 = "11b") do not operate. figure 13 -20 . halftone signal control register (htcon)
on-screen display s3c880a/f880a 13 - 24 background color and halftone function mode r g b blank osdht r g b blank osdht colcon.7 = "0", if osdcol.0 = "0", colcon = 29h, htcon.3-.2 ="10b" frame background: disable, frame halftone: disable, character background: enable with blue color, character background halftone: enable if osdcol.0 = "0", colcon = a1h, htcon.3-.2 ="11b" frame background: enable with green coler, frame halftone: enable, character background: enable with blue color, character background halftone: enable background color: blue character color: red frame background color: green scan figure 13 -21 . halftone or character backgound signal output
s3c880a/f880a on-screen display 13 - 25 osd field control register (osdfld) osd field control register helps recognizing whether the current field is an even field or an odd one, in a tv signal frame. this control register must be defined for a current field recognition of v-sync and h-sync entering the s3c880a/f880a. in order to recognize an even field, osdfld.0?.3 defines the range starting from the point of v-sync edge, where h-sync must be present. if h-sync exits within the range, the field is recongnized as an even field. osdfld.4 defines when h-sync must be detected. if it is set to ?0?, the existence of h-sync is detected within the range set by osdfld.0?.3 before v-sync is input. if it is set ?1?, it is detected after v-sync is input. osdfld.5 describes whether the current, field input by the field control which is set by osdfld.0?.3 and osdfld.4 is an even field or an odd one. osd field control register (osdfld) e5h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 not used field data (read only): 0 = even field 1 = odd field even field range: 0000 = not used 0001 = f cpu /16 x 1 0010 = f cpu /16 x 2 0011 = f cpu /16 x 3 0100 = f cpu /16 x 4 0101 = f cpu /16 x 5 0110 = f cpu /16 x 6 0111 = f cpu /16 x 7 1000 = f cpu /16 x 8 1001 = f cpu /16 x 9 1010 = f cpu /16 x 10 1011 = f cpu /16 x 11 1100 = f cpu /16 x 12 1101 = f cpu /16 x 13 1110 = f cpu /16 x 14 1111 = f cpu /16 x 15 h-sync detect position select: 0 = detect h-sync before v-sync 1 = detect h-sync after v-sync figure 13-22. osd field control register (osdfld)
on-screen display s3c880a/f880a 13 - 26 field detect by osdfld control when control register set is osdfld.0-.3 = ?1010b?, osdfld.4 = 0 f c pu / 16 x 10 v-sync blank even filed odd filed v-sync input h-sync input h-sync input figure 13-23. field detect in before v-sync f c pu / 16 x 10 v-sync blank even filed odd filed v-sync input h-sync input v-sync input figure 13-24. field detect in after v-sync
s3c880a/f880a on-screen display 13 - 27 osd palette color control osd palette color mode registers (osdpltr, osdpltg, osdpltb) osd palette color mode register r, g, b controls the color of osd r, g, b output. osdpltr1, osdpltr2, osdpltg1, osdpltg2, osdpltb1, and osdpltb2 are composed of 8 bits each, in which the combinations of bit0-bit1, bit2-bit3, bit4-bit5, bit6-bit7 of osdpltx1 (x = r, g, b) define color mode 0 to 3 and bit0-bit1, bit2-bit3, bit4-bit5, bit6-bit7 of osdpltx2 (x = r, g, b) define color mode 4 to 7, respectively. each color mode can express upto 64 color by combing the six registers (osdpltr1, osdpltr2, osdpltg1, osdpltg2, osdpltb1, osdpltb2). as one color mode can select one color out of 64 choices, and there are 8 color modes, a total of 8 colors can be displayed at time. for example, when combining color mode 0, each of osdpltr1.0-1, and osdpltb1.0-1 can produce 4 kids of red level, which can be multiplied upto 64 combinations. each 2 bits define a color mode make 4 color levels available. when the standard lighting is 100%, the value "00b" means disabled, "01b" means 33% and "10b" means 66% of the standard light level. osd palette color mode register r1 (osdpltr1) e6h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 osd mode 3 red level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 2 red level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 0 red level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 1 red level 00 = disable 01 = 33% 10 = 66% 11 = 100% figure 13-25. osd palette color mode register r1 (osdpltr1)
on-screen display s3c880a/f880a 13 - 28 osd palette color mode register r2 (osdpltr2) e7h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 osd mode 7 red level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 6 red level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 4 red level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 5 red level 00 = disable 01 = 33% 10 = 66% 11 = 100% figure 13-26. osd palette color mode register r2 (osdpltr2)
s3c880a/f880a on-screen display 13 - 29 osd palette color mode register g1 (osdpltg1) e8h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 osd mode 3 green level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 2 green level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 0 green level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 1 green level 00 = disable 01 = 33% 10 = 66% 11 = 100% figure 13-27. osd palette color mode register g1 (osdpltg1) osd palette color mode register g2 (osdpltg2) e9h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 osd mode 7 green level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 6 green level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 4 green level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 5 green level 00 = disable 01 = 33% 10 = 66% 11 = 100% figure 13-28. osd palette color mode register g2 (osdpltg2)
on-screen display s3c880a/f880a 13 - 30 osd palette color mode register b1 (osdpltb1) eah, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 osd mode 3 blue level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 2 blue level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 0 blue level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 1 bluelevel 00 = disable 01 = 33% 10 = 66% 11 = 100% figure 13-29. osd palette color mode register b1 (osdpltb1) osd palette color mode register b2 (osdpltb2) ebh, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 osd mode 7 blue level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 6 blue level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 4 blue level 00 = disable 01 = 33% 10 = 66% 11 = 100% osd mode 5 bluelevel 00 = disable 01 = 33% 10 = 66% 11 = 100% figure 13-30. osd palette color mode register b2 (osdpltb2)
s3c880a/f880a on-screen display 13 - 31 osd space color control register (osdcol) rgb output selection s3c880a/f880a has two rgb output mode: digital mode and analog mode. in digital mode, osdcol.0 must be set to 0. rgb output has two levels, vss and vdd. eight colors can be produced: black, blue, green, cyan, red, magenta, yellow and white. osd palette color control registers, osdpltr1, osdpltr2, osdpltg1, osdpltg2, osdpltb1, and osdpltb2, are not used in this mode. in analog mode, osdcol.0 must be set to 1. r.g.b output color bright can be selected among four levels respectively. 64 colors can be selected by setting osd palette color control registers, osdpltr1, osdpltr2, osdpltg1, osdpltg2, osdpltb1, and osdpltb2. in one display row you can select 8 colors, color mode 0?7, by setting colbuf.2?.0. the color selected by color mode 0?7 can be changed in every display row. inter-row space halftone inter-row spacing is the distance (in h-sync pulses) between two rows of displayed characters and can be changed by setting rowcon.2-.0. also halftone character can be changed for this inter-row spacing. for osdcol.1=0, halftone function of inter-row space region is the same as that of the character background region. that is, if the halftone function of character background region is enabled by setting htcon.3 to ?1?, the halftone function of inter-row space region is enabled. when htcon.3 is set to ?1?, halftone function of character background is enabled regardless of the value of htcon.2. for osdcol=1 (depend on frame background halftone), inter-row space halftone function is enabled when the value of htcon.3 and htcon.2 are set to "1". inter-row space color inter-row space color depends on the character background color and frame background color by colcon. when osdcol.2 is ?0?, inter-row space color depends on the current character background color; when osdcol.2 is ?1?, inter-row space color depends on the current frame background color. fringe dot size selection 1 dot (when osdcol.3 is ?0?) is a fringe size, which is set by osdfrg1 and osdfrg2. for 1/2 dot fringe size (when osdcol.3 is ?1?), fringe function is set by 1/2 dot unit. in the interlaced scan, even field line and odd field line are added to form 1 dot of length. if character size of length is x1 or x3 in the 1/2 dot fringe size, blinking can occur. so, 1 dot fringe size method is recommended. inter character smoothing control if inter character smoothing is enabled (when osdcol.4 is ?1?), adjacent character is considered as one character and smoothing function is enabled.
on-screen display s3c880a/f880a 13 - 32 osd space color control register (osdcol) e4h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 not used inter character smoothing control bit (note) : 0 = disable inter character smoothing 1 = enable inter character smoothing rgb output selection bit: 0 = digital rgb output (disable palette color mode) 1 = analog rgb output (enable palette color mode) fringe dot size selection bit: 0 = 1 dot 1 = 1/2 dot inter-row space halftone 0 = depend on character background halftone 1 = depend on frame background halftone inter-row space color 0 = depend on character background color 1 = depend on frame background color figure 13-31. osd space color control register (osdcol)
s3c880a/f880a on-screen display 13 - 33 osd border/fringe function fringing function the fringing function is used to display a character with a fringe (fringe means shadowed character at bottom and right direction) width is 1 or 1/2 dot in a different color from that of the character. for all character size, fringe width is 1 or 1/2 dot by set of osdcol.3. when a character is displayed with the maximum of 18 vertical dots and 16 horizontal dots, the fringe exceeds right and bottom of the character display area. the exceeded fringe can be displayed; however , display characters have higher priority to fringe. in this case, if you want to display both fringe and character, you should set inter-row space and inter-column space. when 1dot fringe function is selected, you should set minimum two dots of inter-row space or inter-column space. when 1/2 dot fringe function is selected, you should set minimum one dot of inter-row space or inter-column space. fringing is enabled for each line by setting each bit of osdfrg1 and osdfrg2 to ?1? when osdfrg2.7=?1?. three bits of osdfrg2.6-.4 are control border color. a color for fringe is specified common to selected row and a color for fringe to each row are controlled differently. note: when vertical size x1 and x3 in 1/2 fringe enabled, the flickering may be generated. because vertical 1 dot means even and odd field, that is 1/2 dot is even or odd field area. so interlace scan tv system, you can see the flickering. border function the border function is used to display a character with a border (border means shadowed at all character boundary) width is 1/2 dot in a different color from that of the character. for all character size, border width is 1/2 dot. when a character is displayed with the maximum of 18 vertical dots and 16 horizontal dots, the fringe exceeds right and bottom of the character display area. the exceeded border can be displayed; however , display characters have higher priority to fringe. in this case, if you want to display both border and character, you should set inter-row space and inter-column space over minimum one dot. border is enabled for each line by setting each bit of osdfrg1 and osdfrg2 to ?1? when osdfrg2.7=?0?. three bits of osdfrg2.6-.4 are control border color. a color for border is specified common to selected row and a color for fringe to each row are controlled differently. note: when vertical size x1 and x3, the flickering may be generated. because vertical 1 dot means even and odd field, that is 1/2 dot is even or odd field area. so interlace scan tv system, you can see the flickering.
on-screen display s3c880a/f880a 13 - 34 osd fringe/border control register 1 (osdfrg1) e0h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 fringe/border function enable bit: 0 = disable fringe/border function at row n (n = 0-7) 1 = enable fringe/border function at row n (n = 0-7) figure 13-32. osd fringe/border control register 1 (osdfrg1) lsb msb .7 .6 .5 .4 .3 .2 .1 .0 fringe/border color selection bits: (.6 = red, .5 = green, .4 = blue) fringe/border color .4 osdcol.0 = 0 osdcol.0 = 1 .5 .6 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 black blue green cyan red magenta yellow white color mode 0 color mode 1 color mode 2 color mode 3 color mode 4 color mode 5 color mode 6 color mode 7 osd fringe/border control register 2 (osdfrg2) e1h, set 1, bank 1, r/w fringe/border function enable bit: 0 = disable fringe/border function at row n (n = 8-11) 1 = enable fringe/border function at row n (n = 8-11) fringe or border selection bit: 0 = border function select 1 = fringe function select figure 13-33. osd fringe/border control register 2 (osdfrg2)
s3c880a/f880a on-screen display 13 - 35 osd smooth fucntion smoothing function the smoothing function is used to make characters look smooth. enabling smoothing displays 1/4 dot between two dots connecting corner to corner within a character. smoothing is enabled by setting each bit of osdsmh1 and osdsmh2 to ?1?. a smooth is specified common to selected row. osd smooth control register 1(osdsmh1) e2h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 row 0 smooth function enable bit: 0 = disable smooth function at row 0 1 = enable smooth function at row 0 row 1 smooth function enable bit: 0 = disable smooth function at row 1 1 = enable smooth function at row 1 row 2 smooth function enable bit: 0 = disable smooth function at row 2 1 = enable smooth function at row 2 row 3 smooth function enable bit: 0 = disable smooth function at row 3 1 = enable smooth function at row 3 row 7 smooth function enable bit: 0 = disable smooth function at row 7 1 = enable smooth function at row 7 row 6 smooth function enable bit: 0 = disable smooth function at row 6 1 = enable smooth function at row 6 row 5 smooth function enable bit: 0 = disable smooth function at row 5 1 = enable smooth function at row 5 row 4 smooth function enable bit: 0 = disable smooth function at row 4 1 = enable smooth function at row 4 figure 13-34. osd smooth control register 1 (osdsmh1)
on-screen display s3c880a/f880a 13 - 36 osd smooth control register 2 (osdsmh2) e3h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 row 8 smooth function enable bit: 0 = disable smooth function at row 8 1 = enable smooth function at row 8 row 9 smooth function enable bit: 0 = disable smooth function at row 9 1 = enable smooth function at row 9 row 10 smooth function enable bit: 0 = disable smooth function at row 10 1 = enable smooth function at row 10 row 11 smooth function enable bit: 0 = disable smooth function at row 11 1 = enable smooth function at row 11 not used figure 13-35. osd smooth control register 2 (osdsmh2) (a) smoothing (b) bordering (c) priority of smoothing and bordering (d) fringing (1 dot) figure 13-36. smoothing/fringing/priority of smoothing and fringing
s3c880a/f880a on-screen display 13 - 37 f programming tip ? row interrupt function this example shows the effect of the control register setting excluding the htcon.5,4,1,0 and dspcon 3,0 occurs in the next row. the sample program should meet the following specifications : 1. the character size of the row 2 must be double-sized ( 2). 2. the character size of the other rows must be normal ( 1). r0 = 10h v-sync interrupt sb1 dspcon #01h chacon #00h htcon #32h iret osd row interrupt sb1 push r0 r0 dspcon and r0, #0f0h chacon #50h pop r0 yes chacon #00h htcon #23h iret no figure 13 -37 . decision flowchart for row interrupt function programming tip
on-screen display s3c880a/f880a 13 - 38 f programming tip ? row interrupt function (continued) vsync_int: sb1 ; select bank 1 ld dspcon,#01h ; osd on, h/v sync rising edge ;this is vsync interrupt service routine. interrupt_end: ld htcon, #32h ; pending bit clear iret row_int: sb1 ; select bank 1 push r0 ; stack ? r0 ld r 0,dspcon ; r0 ? dspcon data and r 0,#0f0h ; 11110000b, bit0-bit3 clear cp r 0,#10h ; row 1 interrupt? jr ne, no_char_change ld chacon,#50h ; double size character at row 2 jr t, row_interrupt_end no_char_change: ld chacon, #00h ; x1 size character except row 2 row_interrupt_end: pop r0 ld htcon, #23h ; pending bit clear iret
s3c880a/f880a on-screen display 13 - 39 f programming tip ? writing character code and color data to the osd video ram this example shows how to write character code and color data to the osd video ram. the sample program performs the following operations: 1. write red character 'a' (code 0a, for example) to the video ram from address 00h to 77h . 2. write green character 'b' (code 0b, for example) to the video ram from address 78h to 0f b h. sb1 ; selec t bank 1 ld dspcon,#0f9h ; osd module on; negative sync trigger is selected ld osdcol,#0 ; digital rgb selection ld pp,#11h ; select osd video ram page (page 1) srp0 #0c0h ; select common working register area ld colbuf,#04h ; load color buffer (red color) clr r0 ; load starting address (00h) to r0 osdlp1 ld @r0,#0ah ; write red character a to video ram address 00h ?77h inc r0 ; " cp r0,#77h ; " jp ule,osdlp1 ; " ld colbuf,#02h ; load green color code (02h) to the color buffer osdlp2 ld @r0,#0bh ; write green character b to ram address 78h ?0f b h inc r0 ; " cp r0,#0f b h ; " jp ule,osdlp2 ; " sb0 ; select bank 0 f programming tip ? osd fade function; line and row counters this example is a continuation of the previous osd example in which character code and color data were written to the video ram. assuming a timer a interrupt interval of 2 milliseconds, the sample program should meet the following specifications: 1. if bit fade (r4.0) is set, then enable the fade function. 2. interval time between two lines = 20 ms. (the flag 'intval' is set at 20-ms intervals in the timer a service routine.) 3. fade direction is 'fade after '.
on-screen display s3c880a/f880a 13 - 40 yes ("1") fade = "1"? fadecon f_strt = "1"? f_strt "1" exit intval = "1"? rowcnt #00h linecnt #00h f_strt "1" no ("0") exit no ("0") no ("0") linecnt linecnt + #1 intval "1" linecnt = #19? yes ("1") linecnt #00h rowcnt rowcnt + 1 n (< #19) y (> #19) = rowcnt = #11? fade 0 disable fade function enable fade n (< #12) osd on exit yes (initial) figure 13 -38 . decision flowchart for fade function programming tip
s3c880a/f880a on-screen display 13 - 41 f programming tip ? osd fade function; line and row counters (continued) rowcnt equ 6 linecnt equ 7 fade eq u 0 f_strt equ 1 int_cnt equ 5 intval equ 2 sb1 ; select bank 1 ld pp,#11h ; select osd video ram page (page 1) srp0 #0c0h ; rp0 ? 0c0h (common working register area) btjrf exit1,r4.fade ; if flag fade = "0", then jump to exit1 btjrt fad1,r4.f_strt ; if f_strt = "1", then jump to fad1 btjrf exit,r4.intval ; if intval = "1", then jump to ext inc rlinecnt ; line counter ? line counter + 1 bitr r4.intval ; intval ? "0" cp rlinecnt,#13h ; line counter 3 19? jp ult,fad2 ; if li ne counter < 19, then jump to fad2 clr rlinecnt ; line counter ? "0" inc rrowcnt ; row counter ? row counter + 1 cp rrowcnt,#0 d h ; row counter < 11? jp ult,fad2 ; if row 1 2 , then jump to fad2 ld r1,#0f1h ; if row > 1 2 , then finish the fade function ld r2,@r1 bitr r2.6 ; fade disable ld @r1,r2 fad3 ld dspcon,#0f9h ; osd module on jr t,exit (continued on next page)
on-screen display s3c880a/f880a 13 - 42 f programming tip ? osd fade function; line and row counters (continued) fad1 clr rrowcnt ; row counter (r6) ? 0h cl r rlinecnt ; line counter (rn) ? 0h bits r4.f_strt fad2 ld r2,chacon ; r2 ? chacon and r2,#0f0h ; clear the fade row address or r2,rrowcnt ; load new fade row address to r2 ld chacon,r2 ; chacon ? r2 inc r1 ; r1 ? 0f1h (fade line address) ld r2,rlinecnt ; r2 ? new fade line address or r2,#60h ; enable fade function, select fade after ld fadecon,r2 jr t,fad3 exit1 bits r4.f_strt exit sb0 ; select bank 0 taint push pp push rp0 ld pp,#11 ; select video ram page (page 1) srp0 #0c0h ; rp0 ? 0c0h inc rint_cnt ; interval counter ? interval counter + 1 cp rint_cnt,#0ah ; interval counter 10? (has 20 ms elapsed?) jp ule,ta1 ; if yes, then jump to ta1 clr rint_cnt ; 20 ms has elapsed, so clear interval counter bits r4.intval ; intval ? "1" ta1 nop pop rp0 pop pp iret
s3c880a/f880a on-screen display 13 - 43 f programming tip ? manipulating osd character colors; halftone function this example is a continuation of the previous osd examples. following the second sample program, red character a is in the video ram address 00h?77h and green character b has been written to addresses 78h?0efh. the program performs the following additional actions: 1. change the color of character 'a' to white. 2. change the color of character 'b' to its complementary color. 3. enable the halftone function for character 'b'. sb1 ; select bank 1 ld pp,#11h ; select video ram page (page 1) srp0 #0c0h ; rp0 ? 0c0h (common working register area) ld colbuf,#0f h ; color buffer ? white color code (07h) , character ; background enable clr r0 ; r0 (video ram address) ? 00h osdlp1 ld @r0,#0ah ; video ram (00h ?77h) ? white 'a' inc r0 ; " cp r0,#77h ; " jp ule,osdlp1 ; " ld r2,colbuf ; r2 ? color buffer (color of character in address 78h) com r2 ; r2 ? (not r2) and r2,#0 f h ; mask out bit 7 through bit 3 of r2 ld colbuf,r2 ; color buffer ? complementary color of the character ; in address 78h ld dspcon ,#0f9h ; osd module on; negative sync trigger selected (continued on next page)
on-screen display s3c880a/f880a 13 - 44 f programming tip ? manipulating character colors; halftone function (continued) halftone call halftone1 ; halftone signal control halftone1 push pp ; stack ? pp push rp0 ; stack ? rp0 push flags ; save flags to stack sb1 ; select bank 1 ld pp,#11h ; page 1 selected srp0 #20h ; rp0 ? 20h (working register area) clr r0 ; r0 ? 00h loop_halftone ld htcon,#02h ; disable halftone control register ; enable v-sync interrupt ld dspcon,#09h ; enable osd; select negative sync trigger ld r1,@r0 ; video ram zero address inc r0 cp r0,#0 fb h ; video ram end? jp ugt,end_halftone tm colbuf ,# 08 h ; check colbuf.3 (character background enable?) jr z,loop_halftone ld htcon,#0ah ; enable halftone ; enable v-sync interrupt ld dspcon,#0dh ; halftone output mode ; select negative sync trigger ; no line is double size jp t,loop_halftone end_halftone pop flags ; restore flag values from stack pop rp0 ; restore register pointer 0 value pop pp ; restore page pointer ret ; return
s3c880a/f880a on-screen display 13 - 45 f programming tip ? osd character size, background color, and display position this example is a continuation of the previous osd examples. it performs the following additional actions: 1. change the character size to horizontal 3 and vertical 2. 2 . enable character background color to the complementary co lor of the character code in address 0efh of the video ram. 3 . enable the frame background; select the color cyan. 4 . set top margin to 16h, inter-row spacing to 1h, left margin to 24 dots, and inter-column spacing to three (3) dots. sb1 ; select bank 1 ld pp,#11h ; select video ram page (page 1) srp0 #0c0h ; select common working register area ld colcon,#0 ; digital rgb selection ld chacon,#60h ; horizontal 3, vertical 2 for character size ld fadecon,#00h ; disable the fade function ld r owcon,#21h ; top margin ? 16h, inter-row space ? 1h ld clmcon,#1bh ; left margin ? 24 dots, inter-column space ? 3 dots ld r3,colbuf ; r3 ? color of the character in address 0efh com r3 ; r3 ? not r3 and r3,#07h ; mask out bit 7 through bit 3 of r3 or r3,#0b8h ; r3 ? cyan frame background color ld colbuf,r3 ; enable character and frame background color ld dspcon,# 09 h ; falling edge sync trigger, osd on sb0 ; select bank 0 f programming tip ? helpful hints about colbuf and osd character code 0 when working with the osd module, please note the somewhat unusual characteristics of the color buffer register (colbuf) and the osd character code 0: ? the color buffer register, colbuf ( f7 c , set 1, bank 1) provides a somewhat unusual method for manipulating character color data. ? osd character code 0 produces a no-display and no-background condition, regardless of the font coding used.
on-screen display s3c880a/f880a 13 - 46 notes
s3c880a/f880a a/d converter 14 - 1 14 analog-to-digital converter overview the 8-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 8-bit digital values. the analog input level must lie between the v dd and v ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d/a converter logic (resistor string type) ? adc control register (adcon) ? four multiplexed analog data input pins (adc0?adc3) ? 8-bit a/d conversion data output register (addata) to initiate an analog-to-digital conversion procedure, you write the channel selection data in the a/d converter control register adcon to select one of the four analog input pins (adcn, n = 0?3) and set the conversion start or enable bit, adcon.0. the read-write adcon register is located at address fah. during a normal conversion, a/d c logic initially sets the successive approximation register to 80h (the approximate half-way point of an 8-bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 8-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.5?4) in the adcon register. to start the a/d conversion, you should set a the enable bit, adcon.0. when a conversion is completed, adcon.3, the end-of-conversion (eoc) bit is automatically set to 1 and the result is dumped into the addata register where it can be read. the a/d converter ten enters an idle state. remember to read the contents of addata before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the adc does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the adc0?adc3 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to circuit noise, will invalidate the result.
a/d converter s3c880a/f880a 14 - 2 using a/d pins for standard digital input the adc module's input pins are alternatively used as digital input in port 0 and port 3. the adc0?adc1 share pin names are p3.0?p3.1 and adc2?adc3 share pin names are p0.6?p0.7, respectively. a/d converter control register (adcon) the a/d converter control register, adcon, is located at address fah. only bits 5-0 are used in the s3c880a/f880a implementation. adcon has three functions: ? bits 5?4 select an analog input pin (adc0?adc3). ? bit 3 indicates the status of the a/d conversion. ? bit 2-1 select a c onversion speed. ? bit 0 starts the a/d conversion. only one analog input channel can be selected at a time. you can dynamically select any one of the four analog input pins (adc0?adc3) by manipulating the 2-bit value for adcon.5?adcon.4. a/d converter control register (adcon) fah, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 conversion start bit: 0 = no effect 1 = a/d conversion start analog input pin selection bits: 00 = adc0 (p3.0) 01 = adc1 (p3.1) 10 = adc2 (p0.6) 11 = adc3 (p0.7) not used clock source selection bit: 00 = f osc /16 01 = f osc /8 10 = f osc /4 11 = f osc /2 end-of-conversion status bit: (read only) 0 = a/d conversion is in progress 1 = a/d conversion complete figure 14-1. a/d converter control register (adcon)
s3c880a/f880a a/d converter 14 - 3 internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range av ss to av ref (usually, av ref = v dd ). different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first bit conversion is always 1/2 av ref. a/d converter control register adcon (fah) adcon .5-4 _ control circuit successive approximation circuit clock selector d/a converter av ref av ss adcon .0 (aden) adcon .2-1 adcon .3 (eoc flag) analog comparator conversion result to data bus adc0/p3.0 adc1/p3.1 adc3/p0.7 adc2/p0.6 addata (fbh) figure 14-2. a/d converter circuit diagram .7 .6 .5 .4 .3 .2 addata (fbh) .1 .0 figure 14-3. a/d converter data register (addata)
a/d converter s3c880a/f880a 14 - 4 t con = 50 cpu clock value remains undetermined conversion start eoc addata previous value valid data figure 14-4. s3c880a/f880a a/d converter timing diagram conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 18 clocks to step-up a/d conversion. therefore, total of 50 clocks are required to complete an 8-bit conversion: with an 10 mhz cpu clock frequency, one clock cycle is 100 ns. if each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 8-bits + step-up time (18 clock) = 50 clocks 50 clock x 100 ns = 5 m s at 10 mhz, 1 clock time = cpu clock internal a/d conversion procedure 1. analog input must remain between the voltage range of av ss and av ref . 2. configure the analog input pins to input mode by making the appropriate settings in p3conl and p0conh registers. 3. before the conversion operation starts, you must first select one of the four input pins (adc0?adc3) by writing the appropriate value to the adcon register. 4. when conversion has been completed, (50 cpu clocks have elapsed), the eoc flag is set to ?1 ?, so that a check can be made to verify that the conversion was successful. 5. the converted digital value is loaded to the output register, addata, than the adc module enters an idle state. 6. the digital conversion result can now be read from the addata register.
s3c880a/f880a a/d converter 14 - 5 note: the symbol 'r' signifies an offset resistor with a value of from 50 to 10 0 ohm. v ss S3F880A av ss adc0-adc3 av ref reference voltage input analog input pin r 104 101 v dd v dd figure 14-5. recommended a/d converter circuit for highest absolute accuracy f programming tip ? configuring a/d converter ld p3conl,#00000101b ; p3.1-0 a/d input mode ld p0conh,#01010000b ; p0.7-6 a/d input mode ld adcon,#00000001b ; channel adc0: p3.0/conversion start ad0_chk: tm adcon,#00001000b ; a/d conversion end ? ? eoc check jr z,ad0_chk ; no ld ad0buf,addata ; conversion data ld adcon,#00010001 b ; channel adc1: p3.1/conversion start ad1_chk: tm adcon,#00001000b ; a/d conversion end ? ? eoc check jr z,ad1_chk ; no ld ad1buf,addata ; conversion data
a/d converter s3c880a/f880a 14 - 6 notes
s3c880a/f880a electrical data 1 5- 1 1 5 electrical data overview in this section, s3c880a/f880a electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? i/o capacitance ? a.c. electrical characteristics ? input timing measurement points for t nf1 and t nf2 ? data retention supply voltage in stop mode ? stop mode release timing when initiated by nreset ? main oscillator and l-c oscillator frequency ? clock timing measurement points for x in ? main oscillator clock stabilization time (t st ) ? a/d converter electrical characteristics ? characteristic curves
electrical data s3c880a/f880a 1 5- 2 table 15- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6 .0 v input voltage v i1 p 1 .0?p 1 .5 (open-drain) ? 0.3 to + 7 v v i2 all port pins except v i1 ? 0.3 to v dd + 0.3 output voltage v o all output pins ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for port 1 + 100 total pin current for ports 0, 2 , and 3 + 100 operating temperature t a ? ? 2 0 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 15- 2. d.c. electrical characteristics (t a = ? 2 0 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit input high v ih1 all input pins except v ih2 0.8 v dd ? v dd v voltage v ih 2 x i n , x out 2.7 v input low voltage v il1 all input pins except v il2 ? ? 0.2 v dd v v il2 x in , x out 1.0 v output high voltage v oh i oh = ? 500 a p 0.0?p0.5 , p1. 6 ?p1.7 , p2 r, g, b (digital level) , vblank v dd ? 0.8 ? ? v output low voltage v ol1 i ol = 4 ma p 0.0?p0.5 , p1. 6 ?p1.7 ? ? 0.5 v v ol2 i ol = 1 0 ma p 1.4 ?p1. 5 ? ? 0.8 v ol3 i ol = 2 ma p1.0?p1.3, p 3 .0?p 3.1, p0.6?p0.7 ? ? 0.5 v ol4 i ol = 1 ma r, g, b (digital level) , vblank, p 2 ? ? 0.4 v
s3c880a/f880a electrical data 1 5- 3 table 15- 2. d.c. electrical characteristics (continued) (t a = ? 2 0 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit input high leakage current i lih1 v in = v dd all input pins except i lih2 and i lih3 ? ? 1 a i lih2 v in = v dd , osc in , o sc out 1 0 i lih3 v in = v dd , x in , x out 2.5 10 2 0 input low leakage current i lil1 v in = 0 v all input pins except i lil2 , i lil3 , and nreset ? ? ? 1 a i lil2 v in = 0 v, osc in , osc out ? 1 0 i lil3 v in = 0 v, x in , x out ? 2.5 ? 10 ? 2 0 output high leakage current i loh1 v out = v dd all output pins except i loh2 ? ? 1 a i loh2 v out = 6 v p 1.0?p1.5 1 0 output low leakage current i lol v out = 0 v all output pins ? ? ? 1 a supply current (note) i dd1 normal mode; v dd = 4.5 v to 5.5 v 8-mhz cpu clock ? 7 20 ma i dd2 idle mode; v dd = 4.5 v to 5.5 v 8-mhz cpu clock 4 10 i dd3 stop mode; v dd = 4.5 v to 5.5 v 1 10 a note: supply current does not include the current drawn through internal pull-up resistors or external output current loads.
electrical data s3c880a/f880a 1 5- 4 table 15- 3. input/output capacitance (t a = ? 2 0 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 15- 4. a.c. electrical characteristics (t a = ? 2 0 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit v-sync pulse width t vw ? 4 ? ? s h-sync pulse width t hw ? 3 ? ? s noise filter t nf1 p 1.0 ?p 1.3, h-sync, v-sync ? 3 5 0 ? ns t nf2 nreset ? 1000 t nf3 glitch filter (oscillator block) ? 25 t nf 4 capa ? 5 ? t capa note: f capa = f osc /128. table 15-5. analog r,g,b output (t a = ? 20 c to + 85 c, v dd = 4.75 v to 5.25 v) output voltage (50 k w load) remark v dd = 4.75 v v dd = 5.00 v v dd = 5.25 v data = 11 4.00 v 0.30 v 4.20 v 0.30 v 4.40 v 0.30 v data = 10 3.10 v 0.25 v 3.35 v 0.25 v 3.40 v 0.25 v data = 01 1.90 v 0.20 v 2.00 v 0.20 v 2.10 v 0.20 v data = 00 0.00 v ? 0.65 v 0.00 v ? 0.75 v 0.00 v ? 0.75 v
s3c880a/f880a electrical data 1 5- 5 t nf1l 0.8 v dd 0.2 v dd t nf2h 1t cpu t nf2 figure 15- 1. input timing measurement points for t nf1 and t nf2 table 15-6 . data retention supply voltage in stop mode (t a = ? 20 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2 ? 6 v data retention supply current i dddr stop mode, v dddr = 2.0 v ? ? 5 a notes: 1. supply current does not include the current drawn through internal pull-up resistors or external output current loads. 2. during the oscillator stabilization wait time (t wait ), all the cpu operations must be stopped. execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilization time normal operating mode data retention mode t wait nreset v dd note: t wait is the same as 4096 x 16 x 1/f osc 0.2 v dd figure 15- 2. stop mode release timing when initiated by a nreset
electrical data s3c880a/f880a 1 5- 6 table 15-7 . main oscillator and l-c oscillator frequency (t a = ? 2 0 c + 85 c, v dd = 4.5 v to 5.5 v) oscillator clock circuit conditions min typ max unit crystal x in c1 c2 x out osd block active 5 6 8 mhz osd block inactive 0.5 6 8 ceramic x in c1 c2 x out osd block active 5 6 8 mhz osd block inactive 0.5 6 8 external clock x in x out osd block active 5 6 8 mhz osd block inactive 0.5 6 8 l-c oscillator osc in c1 c2 osc out recommend value; c1 = c2 = 20 pf 5 6.5 8 mhz cpu clock frequency ? 0.032 6.0 8 mhz x in t xh t xl 1/f osc 2.7 v 1.0 v figure 15- 3. clock timing measurement points for x in
s3c880a/f880a electrical data 1 5- 7 table 15-8 . main oscillator clock stabilization time (t a = ? 2 0 c + 85 c, v dd = 4.5 v to 5.5 v) oscillator symbol test condition min typ max unit crystal ? v dd = 4.5 v to 6.0 v ? ? 20 ms ceramic (oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range.) 10 external clock x in input high and low level width (t xh , t xl ) 65 ? 100 ns release signal setup time t srel normal operation ? 1000 ? ns oscillation stabilization wait t wait cpu clock = 8 mhz; stop mode released by nreset ? 8.3 ? ms time ( 1 ) cpu clock = 8 mhz; stop mode released by an interrupt ( 2 ) notes: 1 . oscillation stabilization time is the time required for the cpu clock to return to its normal oscillation frequency after a power-on occurs, or when stop mode is released. 2 . the oscillation stabilization interval is determined by the basic timer (bt) input clock setting.
electrical data s3c880a/f880a 1 5- 8 table 15-9 . a/d converter electrical characteristics (t a = ? 2 0 c to + 85 c, v dd = 4.5 v to 5.5 v, v ss = 0 v) parameter symbol test conditions min typ max unit absolute accuracy v dd = 5.12 v cpu clock = 8 mhz av ref = 5.12 v av ss = 0 v ? ? 2 lsb conversion time (1) t con f osc = 8 mhz 25 ? ? us analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 ? ? m w adc reference voltage av ref ? 2.5 ? v dd v adc reference ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5 v ? ? 10 ua adc block current (2) i adc av ref = v dd = 5 v ? 1 3 ma av ref = v dd = 5 v power down mode ? 100 500 na notes: 1. 'conversion time' is the time required from the moment a conversion operation starts until it ends. 2. i adc is operating current during a/d conversion.
s3c880a/f880a mecha nical data 16- 1 16 mechanical data overview the s3c880a/f880a microcontrollers are available in 42-pin sip package (42-sdip-600), 44-pin qfp package (44- qfp-1010b) . note : dimensions are in millimeters. 39.50 max 39.10 0 .20 0.50 0.10 1.78 (1.77) 0.51 min 3.30 0.30 3.50 0.20 5.08 max 42-sdip-600 0-15 1.00 0.10 0.25 + 0.10 - 0.05 15.24 14.00 0 .20 #42 #22 #21 #1 figure 16-1. 42-pin sdip package dimensions (42-sdip-600)
mechanical data s3c 880a/f880a 16- 2 44-qfp-1010b #44 note : dimensions are in millimeters. 10.00 0.2 13.20 0.3 10.00 0.2 13.20 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 max 0.80 0.20 0.05 min 2.05 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 figure 16-2. 44-pin qfp package dimensions (44-qfp-1010b)
s3c880a/f880a s3c88 0a/f880a mtp 17- 1 17 S3F880A mtp overview the s3c880a/f880a single-chip cmos microcontroller is the mtp flash rom version. it has an on-chip flash rom instead of a masked rom. the flash rom is accessed by serial data format. pwm0/p2.5 pwm1/p2.1 pwm2/p2.2 (sclk) pwm3/p2.3 (sdat) pwm4/p2.4 pwm5/p2.0 t0/p2.6 t0ck/p1.7 adc0/p3.0 adc1/p3.1 adc2/p0.6 adc3/p0.7 test/ test int0/p1.0 int1/p1.1 int2/p1.2 int3/p1.3 p1.4 p1.5 p1.6 osdht/p2.7 S3F880A (42-sdip) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p0.0 p0.1 p0.2 p0.3 p0.4 v ss/ v ss cap.a p0.5 v dd/ v dd nreset/ nreset x out x in v ss1 osc out osc in v-sync h-sync vblank vred vgreen vblue 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 17-1. S3F880A pin assignment (42-sdip)
s3c880a/f880a mtp s 3c880a/f880a 17- 2 p1.3/int3 p1.4 p1.5 p1.6 p2.7/osdht vblue vgreen vred vblank h-sync v-sync nc cap.a p0.5 v dd / v dd nreset/ nreset x out x in v ss1 nc osc out osc in p2.4/pwm4 p2.3/pwm3 p2.2/pwm2 ( sclk ) p2.1/pwm1 (sdat) p2.5/pwm0 p0.0 p0.1 p0.2 p0.3 p0.4 v ss p2.0/pwm5 p2.6/t0 p1.7/t0clk p3.0/adc0 p3.1/adc1 p0.6/adc2 p0.7/adc3 test /test p1.0/int0 p1.1/int1 p1.2/int2 S3F880A (44-qfp) 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 figure 17-2. S3F880A pin assignment (44-qfp)
s3c880a/f880a s3c88 0a/f880a mtp 17- 3 table 17-1. descriptions of pins used to read/write the flash rom (S3F880A) main chip during programming pin name pin name pin no. i/o function p2.3 (pin 4) sdat 4 (43) i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p2.2 (pin 3) sclk 3 (42) i/o serial clock pin (input only pin) test v pp (test) 13 (8) i 0 v: operating mode 5 v: test mode 12.5 v: flash rom writing mode reset reset 33 (29) i 5 v: operating mode, 0 v: flash rom writing mode v dd /v ss v dd /v ss 34/30, 37 (30/26, 34) i logic power supply pin. note: parentheses indicate pin number for 44-qfp package.
s3c880a/f880a mtp s 3c880a/f880a 17- 4 notes
s3c880a/f880a development tools 1 8- 1 1 8 development tools overview samsung provides a powerf u l and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7 , s3c8 , s3c9 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for i n -circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed com ple tely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm88 the sasm88 is an relocatable assembler for samsung's s3c8 -series microcontrollers. the sasm88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm88 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask ro m. when generating the rom code . ( obj file) by hex2rom, the value 'ff' is filled into the unused rom area up to the maximum rom size of the targe t device automatically.
development tools s3c880a/f880a 1 8- 2 target boards target boards are available for all s3c8 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. smds2+ rs-232c pod probe adapter tb880a target board ibm-pc at or compatible prom/otp writer unit bus ram break/display unit trace/timer unit sam8 base unit power supply unit target application system eva chip figure 1 8-1 . smds product configuration (smds2+)
s3c880a/f880a development tools 1 8- 3 tb8 80a target board the tb8 80a target board is used for the s3c880a/f880a microcontroller s . it is supported with the smds2+. the tb8 80a target board can also be used for s3c880a/f880a . tb880a sm1342a 100-pin connector 25 1 reset j101 42 1 144 qfp s3e8800 eva chip 40-pin connector gnd v cc 21 22 74hc10 to user_v cc off on 74hc4050 74hc4050 idle stop 27c512 external triggers ch1 ch2 smds2+ smds2 cn + + mds eprom 1 l-c clock figure 1 8-2 . tb8 80a target board configuration
development tools s3c880a/f880a 1 8- 4 table 1 7- 1. power selection settings for tb8 80a 'to user_vcc' settings operating mode comments to user_v cc off on target system smds2+ tb880a v cc v ss v cc the smds2+ main board supplies v cc to the target board (evaluation chip) and the target system. to user_v cc off on target system smds2+ external v cc v ss v cc tb880a the smds2+ main board supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note: the following symbol in the 'to user_vcc' setting column indicates the electrical short (off) configuration:
s3c880a/f880a development tools 1 8- 5 smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 1 7-2 . the smds2 + tool selection setting 'sw1' setting operating mode smds2 smds2+ r/w r/w smds2+ target system osd font rom selection table 17-3. osd font rom selection setting 'sw2' setting comments mds eprom eprom (27c512) is used for osd font rom mds eprom not used
development tools s3c880a/f880a 1 8- 6 table 1 7-4 . using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions.
s3c880a/f880a development tools 1 8- 7 j101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50-pin dip connector pwm0/p2.5 pwm1/p2.1 pwm2/p2.2 (sclk) pwm3/p2.3 (sdat) pwm4/p2.4 pwm5/p2.0 t0/p2.6 t0ck/p1.7 adc0/p3.0 adc1/p3.1 adc2/p0.6 adc3/p0.7 v ss int0/p1.0 int1/p1.1 int2/p1.2 int3/p1.3 p1.4 p1.5 p1.6 osdht/p2.7 nc nc nc nc p0.0 p0.1 p0.2 p0.3 p0.4 v ss cap.a p0.5 v dd/ v dd nreset/ nreset n.c n.c v ss osc out osc in v-sync h-sync vblank vred vgreen vblue nc nc nc nc figure 1 7-3 . 50 -pin dip connector j101 for tb8 80a target board 50-pin dip connector target system 42-sdip conversion pcb j101 1 50 25 26 part name: ap42sd order cods: sm6538 1 50 25 26 1 42 21 22 s3c880a figure 1 7-4 . s3c880a/f880a probe adapter for 42 - s dip package
development tools s3c880a/f880a 1 8- 8 notes

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